Synchronous static random access memory

Details Synchronous static random access memory Synchronous static random access memory

1992-10-22

1994-05-03

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36518905, 365203, 365233, 36518907, G11C 700

Patent

active

053093950

ABSTRACT:
Maximum operating speed is achieved in an array of memory cells by performing both read and write operations within a single memory cycle. As outgoing data are read from the memory cells, incoming data are stored immediately in those cells. Once data are read from the memory cells, a latch signal is generated to trigger latching of the read data for output to a data bus. The same latch signal that is used to latch the read data initiates the writing of new data to the memory cells. Use of a single latch signal in this manner ensures that new data are not written to the memory cells until the existing data has been read from those cells.

REFERENCES:
patent: 4829471 (1989-05-01), Banerjee et al.
patent: 4849937 (1989-07-01), Yoshimoto
Chu, S. T. et al., "A 25-ns Low-Power Full-CMOS 1-Mbit (128K.times.8) SRAM," IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1078-1084.
deWerdt, R. et al., "A 1M SRAM With Full CMOS Cells Fabricated In A 0.7$ mu $M Technology," IEDM, 1987, pp. 532-534.
Nakagome, Y. et al., "A 1.5V Circuit Technology for 64 Mb DRAMs," 1990 Symposium on VLSI Circuits, Honolulu, Jun. 7-9, 1990, pp. 17-18.
Blalock, T. N. et al., "An Experimental 2T Cell RAM With 7 NS Access Time At Low Temperatures," 1990 Symposium on VLSI Circuits, Honolulu, Jun. 7-9, 1990, pp. 13-14.
Sasaki, K. et al., "A 9-ns 1-Mbit CMOS SRAM," IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1219-1225.
Seevinck, E., "A Current Sense-Amplifier For Fast CHMO SRAMs," 1990 Symposium on VLSI Circuits, Honolulu, Jun. 7-9, 1990, pp. 43-44.
Seevinck, E. et al., "Current-Mode Techniques for High-Speed VLSI Circuits With Application To Current Sense Amplifier for CMOS SRAM's," IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, pp. 525-536.

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