Synchronous SRAMs having multiple chip select inputs and a stand

Details Synchronous SRAMs having multiple chip select inputs and a stand Synchronous SRAMs having multiple chip select inputs and a stand

1998-11-23

1999-12-28

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

711 2, 711104, 711169, 36523003, G06F 1200

Patent

active

06009494&

ABSTRACT:
A synchronous SRAM module comprises first and second SRAM chips. Each SRAM chip has three chip enable inputs. A module enable and memory selection circuit is coupled to the two SRAM chips to perform the dual tasks of (1) selectively enabling or disabling both SRAM chips and (2) choosing either the first or second SRAM chips for access. The SRAM module can also be placed in a pipelining mode where external signals from a microprocessor are ignored to facilitate internal operation, such as burst reads. A synchronous burst SRAM device employed in the SRAM module is also described.

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