Synchronous SRAM having pipelined enable

Details Synchronous SRAM having pipelined enable Synchronous SRAM having pipelined enable

1999-08-04

2001-06-26

Peikari, B. James (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S104000, C711S152000, C710S035000

Reexamination Certificate

active

06253298

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application is a continuation-in-part of a U.S. patent application filed Oct. 5, 1995, titled “Synchronous SRAM Having Global Write Enable”, assigned to Micron Technology, Inc. by inventor J. Thomas Pawlowski, and incorporated herein by reference, which in turn is a continuation-in-part of U.S. patent application Ser. No. 08/391,725, filed Feb. 21, 1995, titled “Synchronous SRAMs Having Logic Circuitry for Memory Expansion”.
TECHNICAL FIELD
This invention relates to synchronous SRAMs (Static Random Access Memories).
BACKGROUND OF THE INVENTION
Synchronous SRAMs are a type of SRAM that is registered and accessed in accordance with externally generated clock signals. The clock signal provides for synchronous operation of the SRAM. An SRAM is typically used as a cache. A cache is a small, fast redundant memory which duplicates frequently accessed information from a main memory, such as a DRAM.
One specific type of synchronous SRAMs is a synchronous burst SRAM which is designed in systems to achieve higher SRAM performance. Synchronous burst SRAMs have an internal counter which facilitates internal addressing of typically two to four addresses for each externally generated address that is loaded into the memory device. The internal “burst” addresses can be generated more rapidly in comparison to externally generating the same addresses and then loading them into the memory device using conventional techniques. Accordingly, the burst SRAMs operate faster and achieve higher performance: A pair of prior art synchronous SRAMs
100
and
102
connected to a 64 bit processor
104
is illustrated in FIG.
1
.
The purpose of burst logic included in the above described synchronous burst SRAM is to facilitate cache line operations. A cache line is typically two or four times the data bus width. For example, in a system including a Pentium (TM) processor, the bus width is 64 bits (i.e.; 8 bytes), and the cache line size is 256 bits (i.e.; 32 bytes). Therefore, when a new cache line is read into or out of the SRAM in a system including a 64 bit processor, such as a Pentium (TM), four bus cycles are required, and a burst sequence of length four is employed. Burst sequences are discussed in greater detail below.
When it is desired to write to the SRAM
100
or
102
, the processor
104
generates a byte enable signal on a byte enable line
106
. The byte enable signal cannot be connected directly to the SRAM
100
or
102
, however, because the byte enable signal from the processor does not distinguish between reads, writes, and other operations such as a snoop cycle.
(Snooping refers to the act of scanning bus activity to see if it is trying to modify information that is duplicated elsewhere. For example, something in cache is a duplicate of data in main memory. If a device tries to modify the data in main memory, it should also be modified in cache so that the data is coherent.)
Cache control logic
107
provides an interface between the synchronous burst SRAMs
100
and
102
, and the processor. The cache control logic
107
is typically implemented in an ASIC (Application Specific Integrated Circuit).
In early SRAMs, one signal controlled writing to the SRAM. In later SRAMs, the write signal was split between bytes (e.g., upper byte and lower byte). A standard has thus developed with respect to control logic for synchronous burst SRAMs that requires one byte write input to the SRAM for every 8 or 9 bit width portion of the SRAM. The processor and the control logic both have an influence on the SRAM, and have different requirements of the SRAM.
A 64 bit processor
104
, such as the Intel (TM) Pentium (TM), provides 8 byte enable outputs BE
0
#-BE
7
# (8 bits per byte). Because the byte enable signal cannot be connected directly to the SRAM
100
or
102
, control logic
107
that interfaces a 64 bit processor requires 8 inputs, illustrated collectively as
108
, to receive the 8 byte enable signals from the processor, and generates 8 byte write outputs, illustrated collectively as
110
. The control logic thus has a total of 16 input/output (IO) lines. The control logic must be fast, making it difficult to implement all of this logic in an ASIC that operates at high frequencies.
The time required for a byte enable signal to travel from the processor into the control logic, propagate through the control logic, s drive through output buffers in the control logic and into the SRAM can induce an extra wait state during write cycles, It would be easier to optimize fewer signals in the control logic ASIC
110
.
It would therefore be desirable to reduce the number of input/output lines in the control logic ASIC
110
.
Further, it is desirable and advantageous for synchronous burst SRAMs to facilitate a microprocessor-related function known as “address pipelining”. In general, a processor attached to the synchronous burst SRAM outputs an address and data strobe signal each time a new address is ready for input into the SRAM device. On occasions, it may i be desirable to delay execution of that new address. For example, in a synchronous burst SRAM, it might be desirable to continue the burst addressing operation before accepting the next external address. Accordingly, the synchronous burst SRAMs must be capable of blocking or delaying operation on the new address (as indicated by the address and data strobe signal from the processor) until the burst operation is completed.


REFERENCES:
patent: 4141068 (1979-02-01), Mager et al.
patent: 4231105 (1980-10-01), Schuller et al.
patent: 4912630 (1990-03-01), Cochcroft, Jr.
patent: 5126975 (1992-06-01), Handy et al.
patent: 5384745 (1995-01-01), Konishi et al.
patent: 5490116 (1996-02-01), Tobita et al.
patent: 5491663 (1996-02-01), Teel
patent: 5544121 (1996-08-01), Dosaka et al.
patent: 5550783 (1996-08-01), Stephens, Jr. et al.
patent: 5602798 (1997-02-01), Sato et al.
patent: 5604884 (1997-02-01), Thome et al.
patent: 5787489 (1998-07-01), Pawlowski
patent: 5809549 (1998-09-01), Thome et al.
patent: 5848431 (1998-12-01), Pawlowski
patent: 6009494 (1999-12-01), Pawlowski
Millman, Jacob, “Microelectronics: Digital and Analog Circuits and Systems”, McGraw-Hill, Inc., pp. 290-291, 1979.*
Sloan, M. E., “Computer Hardware and Organization: An Introduction”, Science Research Associates, Inc., p. 343, 1983.*
Handy, Jim, “The Cache Memory Book”, Academic Press, pp. 122, 201-205, 1993.*
Hennessy et al., “Computer Organization and Design: The Hardware/Software Interface”, Morgan Kaufmann Publishers, Inc. p. B-30, 1994.*
Hitachi America, Ltd., Semiconductor & I.C. Division, “Hitachi's Synchronous Burst, Pipelined 1Mbit (32K×32) SRAM Meets Industry Demand for Economical, Fast Cache Memory Devices for Pentium PCs”, Mar. 13, 1995.
Sony CXK77V3210Q Data Sheet, Rev. 14.0, Oct. 1995.
Horton, Thomas. “Selecting the Right Cache Architecture for High Performance PCs.” Sony Semiconductor Company of America, San Jose, CA. Apr. 1995.
IBM Press Release, “IBM Introduces Fast 1-Megabit SRAM Family.” Jun. 1994.
IBM IBM043614PQKB Data Sheet, May 1994.
Izumikawa, Masanori et al. “A 400MHz, 300mW, 8kb, CMOS SRAM Macro with a Current Sensing Scheme.” Custom Integrated Circuits Conference, IEEE, Feb. 1994.
Nakamura, Kazuyuki et al. “A 220MHz Pipelined 16Mb BiCMOS SRAM with PLL Proportional Self-Timing Generator.” Solid-State Circuits, 1994 41st Conference, Jul. 1994.
Dickenson, Alex et al. “A Fast Pipelined CMOS SRAM.” Tencon '92, IEEE Region 10 Conference, Nov. 1992.
Gowni, Shiva P. et al. “A 9ns, 32k×9 BiCMOS TTL Synchronous Cache RAM with Burst Mode Access.” Proceedings of the IEEE 1992 Custom Integrated Circuits Conference, May 1992.

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