Synchronous SRAM device with late write function

Details Synchronous SRAM device with late write function Synchronous SRAM device with late write function

2001-09-26

2002-08-27

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S154000

Reexamination Certificate

active

06442103

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2001-15143, filed on Mar. 23, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor devices, and more particularly to a synchronous SRAM (Static Random-Access Memory) device having a late write mode.
BACKGROUND OF THE INVENTION
In a semiconductor memory device with double data rate (to be referred to as “DDR” hereinafter) mode, for example, in case of a SRAM, burst type data is transferred (or input/output) in accordance with the rising and falling edges of a signal, for example a system clock. For example, four data input during a write-in operation are stored in a temporary register, and the four data stored therein are written into memory cells following the input of the next write-in command. When data is read during the following cycle, stored data is output from the temporary register so as to output immediately the input data. As well known in this art, when data is written, a DDR SRAM device with “late write mode” capability receives four data successively in accordance with the clock signal of the next cycle, following a write-in command.
It is assumed that the time period for inputting data in the SRAM device is artificially delayed by one-half cycle of clock signal. Since data input for the SRAM device can be completed in one-half cycle, the central processing unit (CPU) can perform other operations during the half cycle of clock signal. Here, since the time period for inputting data is artificially delayed by the half cycle of clock signal, the time period for writing data in a memory cell of SRAM device is also delayed by a half cycle of clock signal. Therefore, it is impossible during this time period to write-in data in memory cells of the SRAM device.
Even though the time period for inputting data is delayed by a half cycle on the basis of the clock signal in order to obtain suitable operation margin for the CPU (or data is input after 1½ cycles), it needs to be obtained enough write-in time into a memory cell.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a SRAM device having late write mode capable of obtaining enough time for writing into a memory cell even though data input is delayed.
According to the present invention, the synchronous memory device of the present invention includes a late write mode of operation, and includes a memory cell array storing data information. A write-in command detector generates a first flag signal indicating receipt of a write-in command when the write-in command is applied to said memory device, detects whether said write-in command is received during successive clock cycles, and generates a second flag signal indicating the receipt of successive write-in commands during successive clock cycles. A data input control signal generator sequentially generates multiple data input control signals synchronized with the clock cycles in response to said first flag signal, the data input control signals being generated following the receipt of said write-in command and thereafter following 1½ clock cycles.
In a preferred embodiment, the synchronous memory device further comprises a first latch circuit for sequentially latching write-in data from external sources in response to said data input control signals; a second latch circuit for latching data latched in said first latch circuit in response to at least one of the data input control signals; and a select circuit for selecting one of said first and second latch circuits in response to said second flag signal.
The data input control signals are preferably sequentially activated during one-half cycle of said clock cycle. The first latch circuit may include first, second, third and fourth flip-flops which are separately controlled by said data input control signals, and the second latch circuit may include fifth, sixth, seventh and eighth flip-flops, wherein said fifth and sixth flip-flops latch outputs of the first and second flip-flops in response to a second data input control signal, respectively, and wherein the seventh and eighth flip-flops latch outputs of the third and fourth flip-flops in response to a fourth data input control signal.
The select circuit preferably selects the first latch circuit when the second flag signal indicates that said write-in command is successively received, and selects the second latch circuit when the second flag signal indicates that another command is received following a write-in command.


REFERENCES:
patent: 6134180 (2000-10-01), Kim et al.
patent: 6337809 (2002-01-01), Kim et al.

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