Synchronous SRAM-compatible memory device including DRAM...

Details Synchronous SRAM-compatible memory device including DRAM... Synchronous SRAM-compatible memory device including DRAM...

2005-01-25

2005-01-25

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S149000, C365S191000, C365S230010, C365S233100

Reexamination Certificate

active

06847573

ABSTRACT:
The synchronous SRAM-compatible memory includes a DRAM array, a data input/output unit, an address input unit, a burst address generating unit, a state control unit, a refresh timer, and a refresh control unit. The data input/output unit controls input and output of data. The address input unit inputs a row address and a column address. The burst address generating unit generates a sequentially varying burst address. The state control unit generates a burst enable signal that enables the burst address generating unit, controls the data input/output unit, and generates a wait indication signal while an access operation of a previous frame is performed with respect to the memory array. The refresh timer generates a refresh request signal activated at regular intervals. The refresh control unit controls the refresh operation with respect to the DRAM array in response to the refresh request signal.

REFERENCES:
patent: 5588130 (1996-12-01), Fujishima et al.
patent: RE35921 (1998-10-01), Harlin et al.
patent: 6392958 (2002-05-01), Lee
patent: 6603704 (2003-08-01), Wilson
patent: 20030198098 (2003-10-01), Fujioka et al.

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