Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2000-05-05
2004-07-13
Tran, Khai (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C327S147000
Reexamination Certificate
active
06763080
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a synchronous signal processing system and, more particularly, to a technique for handling a signal processing system having a plurality of processors operating with different clock signals as a synchronous circuit operating with a single clock signal.
(b) Description of a Related Art
In view of feasibility of larger circuit scale, higher speed operation and circuit design for semiconductor devices, it is desired that a signal processing system including a plurality of processors operating with different clock signals be handled as a synchronous system operating with a single system clock signal.
FIG. 1
shows a timing chart of signals in a typical video signal processor, implemented as a video signal sampling circuit. The video signal sampling circuit samples a video signal based on a system clock signal. The sampled video signal is then supplied to a succeeding stage circuit together with the system clock signal for allowing the succeeding stage circuit to process the sampled video signal.
There is no substantial phase difference between the input clock signal and the output clock signal of the typical video signal sampling circuit. In this case, the signal processing system including the sampling circuit and succeeding signal processing circuits (referred to as data path circuits, hereinafter) for processing the output of the sampling circuit can be designed as a synchronous system operating with the single system clock signal.
In general, a CPU used in a signal processing system has a phase difference between the input clock signal and the output clock signal thereof, wherein the phase difference therebetween is not defined.
FIG. 2
shows another timing chart of signals used in a signal processing system including a CPU. In the signal processing system, the timings of the signals are defined based on the output clock signal supplied from the CPU. Thus, if a plurality of CPUs or processors are disposed in a single system, the design for synchronization is difficult in the system.
Patent Publication JP-A-11-41095 describes a technique for adjusting the phase in a PLL circuit, which is thus indispensable to the system, as recited in the publication. Patent Publication JP-A-5-324868 describes another technique for adjustment of phases between the input clock signal and the output clock signal of a CPU.
Both the publications mentioned above describe techniques for use of a PLL circuit and for delivering a clock signal to the CPU, and do not refer to a synchronization design of a signal processing system including a plurality of CPUs or processors.
FIG. 3
shows a conceivable example of a signal processing system implementing the techniques described in the above publications.
The signal processing system includes a data path circuit (processor)
11
, a CPU
12
, a system clock generator
17
for delivering a system clock signal f
1
, a PLL circuit for generating a first clock signal f
3
in synchrony with the system clock signal f
1
based on the system clock signal f
1
, a set of external interfaces
16
, and a user data logic (UDL) block
14
for receiving/transmitting data using an internal bus. The CPU
12
receives the first clock signal f
3
and delivers data together with a second clock signal f
2
generated in the CPU
12
.
The UDL block
14
includes a first UDL circuit
15
A, a second UDL circuit
15
B and a clock exchanger
18
, and receives and transmits data from/to the external interface
16
, the data path circuit
11
and the CPU
12
by using the first and second UDL circuits
15
A and
15
B. The first UDL circuit
15
A receives/transmits data to the data path circuit
11
based on the first clock signal f
3
, whereas the second UDL circuit
15
B receives/transmits data to the CPU
12
and external interface
16
based on the second-clock signal f
2
, the first and second clock signals f
3
and f
2
being exchanged by the clock exchanger
18
. The data path circuit
11
uses the first clock signal f
3
supplied from the PLL circuit
13
.
The clock exchanger
18
receives the first and second clock signals f
3
and f
2
at terminals Ick
1
and Ick
2
, and functions for exchanging the first and second clock signals Ick
1
and Ixc
2
for the UDL circuits
15
A and
15
B, whereby signal transmission of the data between the data path circuit
11
and the external interface
16
is operated on the first clock signal f
3
and signal transmission of the data between the CPU
12
and the external circuit is operated on the second clock signal f
2
. The data path circuit
11
operates with the first clock signal f
3
for data processing therein.
There is a disadvantage in the conventional signal processing system in that the presence of the clock exchanger
18
increases the circuit scale of the UDL block
14
and thus the circuit scale of the entire system. In addition, the asynchronous configuration of the signal processing system complicates development of a new product for the system during the circuit design and simulation thereof.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a signal processing system including a plurality of signal processors, such as CPU and data path circuit, which operate with different clock signals, which can be treated as a synchronous system operating with a single clock signal.
The present invention provides a signal processing system including a first processing unit for signal processing based on a system clock signal, a PLL circuit for generating a first clock signal based on the system clock signal, a second processing unit for generating a second clock signal based on the first clock signal and signal processing based on the second clock signal, wherein the PLL circuit receives the second clock signal as a feed-back signal to deliver the first clock signal so that a phase difference between the system clock signal and the second clock signal assumes zero.
In accordance with the signal processing system of the present invention, since the phase difference between the system clock signal and the second clock signal assumes zero, the signal processing system including the first and second processing units can be handled as a synchronous circuit which operates with the single system clock signal, without using a clock exchanger.
REFERENCES:
patent: 6141769 (2000-10-01), Petivan et al.
patent: 6349391 (2002-02-01), Petivan et al.
patent: 2-217919 (1990-08-01), None
patent: 2-226824 (1990-09-01), None
patent: 4-140812 (1992-05-01), None
patent: 4-225408 (1992-08-01), None
patent: 5-313785 (1993-11-01), None
patent: 7-106958 (1995-04-01), None
patent: 7-281783 (1995-10-01), None
patent: 8-237214 (1996-09-01), None
patent: 9-34585 (1997-02-01), None
patent: 9-282042 (1997-10-01), None
patent: 10-313349 (1998-11-01), None
patent: 5-324868 (1998-12-01), None
patent: 11-41095 (1999-02-01), None
McGinn & Gibb PLLC
NEC Electronics Corporation
Tran Khai
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