Synchronous sense amplifier

Details Synchronous sense amplifier Synchronous sense amplifier

1982-06-10

1984-11-20

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

For complementary information

365205, G11C 700, G11C 1140

Patent

active

044843119

ABSTRACT:
A circuit for use in controlling a memory cell coupled to a word line W and to first and second bit lines B1 and B2 includes an enabling flip-flop 20 having set terminal S connected to a source of enabling signals and a reset terminal R connected to an OR gate 22; a word line addressing circuit 25 connected to the output of the enabling flip-flop 20 and to the word line W, and having a terminal ADDR for receiving address information; first and second read/write circuits 29 and 30 connected to corresponding first and second bit lines B1 and B2, respectively, each of the read/write circuits 29 and 30 including a control node WRC and an output node SADO; a logic gate 22 having an output coupled to the reset terminal and having input nodes SADO 0 and SADO 1 connected to the corresponding output nodes of the read/write circuits 29 and 30, and an output flip-flop 33 connected the output nodes SADO 0 and SADO 1 of the read/write circuits 29 and 30.

REFERENCES:
patent: 4168539 (1979-09-01), Anderson

Affiliated with

Also associated with

Rating

Synchronous sense amplifier does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronous sense amplifier, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous sense amplifier will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2193584