Synchronous semiconductor memory having read data mask controlle

Details Synchronous semiconductor memory having read data mask controlle Synchronous semiconductor memory having read data mask controlle

1996-12-16

2000-12-05

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711105, 711154, 365194, 365233, G06F 1200

Patent

active

061579920

ABSTRACT:
A read enable signal OEMF activated in response to an input command is applied to an N minus 2 clock shift circuit included in an output control circuit for implementation of ZCAS latency. An output signal of the N minus 2 clock shift circuit and an internal mask instructing signal activated in response to an external mask instructing signal are logically processed and applied to a one-clock shift circuit. According to an output signal OEMQM of one-clock shift circuit, a data output enable signal OEM controlling activation/inactivation of an output buffer circuit is activated/inactivated. Data output controlling portion occupying area of a synchronous dynamic random access memory is reduced and timings of activation/inactivation of data output by different commands are made the same.

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Yuji Sakai et al., "A Synchronous DRAM with New High-Speed I/O Lines Method for the MultiMedia Age", IEICE Trans. Electron., vol. E78-C, Jul. 7, 1995, pp. 782-788.

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