Synchronous semiconductor memory device with multi-bank...

Details Synchronous semiconductor memory device with multi-bank... Synchronous semiconductor memory device with multi-bank...

2000-04-21

2002-04-23

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S042000, C714S718000

Reexamination Certificate

active

06378102

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices, particularly to clock-synchronous semiconductor memory devices inputting/outputting data in synchronization with a clock signal, and more particularly to a multi-bank semiconductor memory device having a plurality of banks inside.
2. Description of the Background Art
In recent years, microprocessors (MPUs) has come to have multiple functions, which enables high speed processing of a bulk of data. Accordingly, a Dynamic Random Access Memory (hereinafter referred to as DRAM) for use as main memory, has come to have an increased memory capacity as the miniaturizing techniques have been developed. The operation speed of the DRAM, however, cannot catch up with the operation speed of the MPU and the performance of the entire processing system is degraded with the bottleneck due to the time required for accessing the DRAM and the cycle time of DRAM. In order to prevent the performance of the processing system from being degraded, a high speed memory called cache memory, normally formed of a Static Random Access Memory (SRAM), is installed between a DRAM and an MPU. Data/instruction frequently used by the MPU are stored in the cache memory and such data/instruction are transferred between the MPU and the cache memory. Only when an instruction/data requested for access by the MPU is not present in the cache memory, the DRAM is accessed. It is highly probable that instructions/data required by the MPU are previously stored in the cache memory, and therefore the frequency of accessing the DRAM can be greatly reduced, thereby preventing the operation speed of the processing system from being lowered.
Since the SRAM for use in the cache memory is more expensive than the DRAM, the configuration having such a cache memory installed is not suitable for relatively inexpensive devices such as personal computers. There is therefore a demand for improving the performance of processing system using inexpensive DRAMs. One solution to this is a synchronous DRAM (hereinafter referred to as SDRAM) which is adapted to transfer data in synchronization with a clock signal such as system clock.
In the SDRAM, an operation mode instruction signal is applied in a command form (a combination of the states of a plurality of control signals) in synchronization with a clock signal. In the SRAM, according to this command, a plurality of bits (such as 8 bits per one IO) are selected at a time and these simultaneously selected bits are sequentially output in synchronization with the clock signal. At the time of data writing, data for writing is sequentially taken and written in a prescribed sequence into memory cells simultaneously selected in synchronization with a clock signal.
In the SDRAM, in synchronization with a rising edge of a clock signal, externally applied control signals forming a command, in other words a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE, and an address signal and data for writing are taken in for executing internal operation. In synchronization with the clock signal, externally applied data is input and data is output. Therefore it is not necessary to secure a margin for a timing for inputting/outputting data, which takes into consideration of skew (offset in timing) of the control signals and address signals. As a result, the timing for initiating internal operation is rendered faster and therefore the cycle time can be reduced, thus permitting accessing at higher speed.
In a processing system such as image processing system the data bits of serial data addresses are sequentially accessed, while in the processing system a plurality of bits at serial memory positions are frequently accessed because of the localization of the process. Therefore, data is input/output in synchronization with a clock signal, the serial accessing time can be the same as that of the clock signal and the average access time can be comparable to that of the SRAM.
In the SDRAM, the concept of multiple banks is further introduced. More specifically, a plurality of banks are provided in the SDRAM. These banks can be activated and inactivated (precharge) almost independently from each other.
In a standard DRAM, a precharge operation must be performed in order to select a new row. DRAM has its internal signal lines dynamically driven, and therefore each signal line has to be maintained at a prescribed potential level at the time of precharging. For precharging, the time called RAS precharging time tRP is usually necessary (since each internal signal line should be returned to a prescribed potential level.) In the standard DRAM, time called RAS-CAS delay time tRCD is necessary. This is because after a row of memory cells have been selected in response to a row address strobe signal /RAS, a column selecting operation must be executed in response to a column address strobe signal /CAS. Column address strobe signal /CAS must be returned to its inactive state at the of the completion of the column selecting operation. In order to select a memory cell on a new page (a row of memory cells), RAS precharge time tRP and RAS-CAS delay time tRCD are necessary, and therefore the cycle time of a standard DRAM is almost twice its accessing time.
However, if a plurality of banks are provided in the SDRAM, and one bank being activated is accessed while another bank is returned to a precharge state (inactive state), that another bank in the precharge state may be accessed without a waiting time period for RAS precharge time tRP. Therefore, alternately or sequentially activating/precharging (inactivating) these banks permits RAS precharge time tRP to be seemingly eliminated, and therefore high speed accessing is allowed. If one bank is accessed as another bank is precharged and activated, data can be written/read out alternately to/from these banks, time loss by RAS precharge time tRP and RAS-CAS delay time tRCD may be eliminated, and therefore data can be written/read at higher speed.
In the above-described conventional SDRAM, a bank is formed using a memory array (memory mat) as a unit. The memory array (memory mat) has a plurality of memory blocks, and in one memory array, each memory block is driven into a selected or inactive state when a corresponding memory array is activated, and the memory blocks in a memory array cannot be activated/inactivated independently from each other. In the conventional SRAM, the number of banks is as few as the number of memory arrays (memory mats) (usually four banks at most). This is because the array structure of a standard DRAM is employed for the array structure of the SDRAM, row/column decoders are installed separately corresponding to each memory array (memory mat), so that these row/column decoders can be driven independently for each memory array (memory mat).
Use of such a conventional SDRAM with a plurality of banks as a main memory for a processing system will be considered. All the banks of the SDRAM are activated at a time, a row (page) of memory cells are maintained in a selected state in each bank. A sense amplifier provided corresponding to each column of memory cells is used as a pseudo cache. If data/instruction requested by the MPU is not stored in the cache memory (at the time of cache miss), it is determined whether or not the data/instruction requested of accessing by the MPU is present in the selected page of the SDRAM (page hit/miss determination). At the time of page hit, the corresponding page is accessed for transferring the block of data/instructions (cache block) to the cache memory, and the data/instruction requested for acess is transferred to the MPU (for read accessing). Therefore, at page hit, it is requested that the block of the data instructions is selected from the page for reading out, and therefore after elapse of CAS access time ta(CAS) (or CAS latency) the necessary data/instruction may be transferred to cache memory and to the MPU (for read accessing).
Meanwhile, in the case of page

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