Synchronous semiconductor memory device with double data rate sc

Details Synchronous semiconductor memory device with double data rate sc Synchronous semiconductor memory device with double data rate sc

1998-03-18

2000-06-20

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

365194, 365241, 36523004, G11C 800

Patent

active

060785462

ABSTRACT:
Disclosed is a synchronous semiconductor device having a double data rate input circuit which allows data to be written in the device in response to a clock signal and a data strobe signal. The input circuit stores a pair of data which is synchronized with either the clock signal or the data strobe signal, thereby processing data at high speed. In case the data strobe is used, data setup and hold window margin is improved.

REFERENCES:
patent: 5726950 (1998-03-01), Okamoto et al.
patent: 5796675 (1998-08-01), Jang

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