Synchronous semiconductor memory device with a write latency con

Details Synchronous semiconductor memory device with a write latency con Synchronous semiconductor memory device with a write latency con

1995-03-02

1996-10-22

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365194, G11C 800

Patent

active

055684459

ABSTRACT:
A semiconductor memory device for processing data in synchronization with a system clock applied from the exterior includes a circuit for generating a write latency control signal, a circuit for generating one active information enlarged signal from a plurality of active information signals generated in response to a column related control signal supplied from the exterior, and a circuit for holding internal operations of a column address counter, a burst length counter and a data transfer switching circuit for a prescribed time in which the active information enlarged signal is in an active state.

REFERENCES:
patent: 4953128 (1990-08-01), Kawai
patent: 5268865 (1993-12-01), Takasugi
patent: 5386385 (1995-01-01), Stephens
patent: 5444667 (1995-08-01), Obara

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