Synchronous semiconductor memory device performing data...

Details Synchronous semiconductor memory device performing data... Synchronous semiconductor memory device performing data...

2001-07-19

2002-07-30

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S203000, C365S189050

Reexamination Certificate

active

06426900

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device and more particularly, to a synchronous semiconductor memory device including a DLL (Delay Locked Loop) circuit for operating in synchronization with an external clock.
2. Description of the Background Art
Requirements for a high speed operation of a synchronous semiconductor memory device have been leveled up in recent years and in order to cope with such leveled-up requirements, a synchronous semiconductor memory device has been developed that performs data input/output in synchronization with an external clock, which is represented by an SDRAM (Synchronous Dynamic Random Access Memory). In a synchronous semiconductor memory device, a DLL circuit for generating a control clock in synchronization with an external clock is included and data input/output is performed at timings in synchronization with the control clock generated.
As a typical example of a specification for a synchronous semiconductor memory device, there is an access time tAC for defining a time period from an output timing determined according to an external clock till data is actually outputted. Generation of the control clock in the DLL circuit, therefore, is required be performed so as to satisfy a specification of the access time period tAC.
FIG. 13
is a timing chart for describing a data output operation in a general synchronous semiconductor memory device.
Referring to
FIG. 13
, a synchronous semiconductor memory device performs a data output operation, taking in a read command supplied externally at a timing in synchronization with an external clock EXTCLK which repeats a combination of a high level (hereinafter simply referred to as H level) and a low level (hereinafter simply referred to as L level) in a constant cycle.
At a time point t
0
, a read command READ for instructing a read operation is inputted according to a combination of signal levels of command control signals represented by a column address strobe signal EXTZCAS in synchronization with a rise timing of the external clock EXTCLK.
If a setting value of a column latency of the synchronous semiconductor memory device is two clock cycles (CL=2), data output to the outside is requested at a time point t
1
when two clock cycles of the external clock EXTCLK elapse after a time point t
0
. Hence, a difference between a time point at which data is actually outputted and the time point t
1
is requested to satisfy a specification for the access time tAC.
A DLL circuit included in the synchronous semiconductor memory device delays the external clock EXTCLK by one clock cycle or a plurality of clock cycles to generate a feedback clock FBCLK. That is, the DLL circuit performs phase control such that the feedback clock FBCLK and the external clock EXTCLK become in phase with each other.
A data output buffer performing data output to the outside operates in response to a control clock DLLCLK generated by DLL. In the inside of the DLL circuit, a phase of the feedback clock FBCLK lags behind the control signal DLLCLK by a replica delay time Tdr.
Therefore, if the replica delay time Tdr is determined in correspondence to a data processing time in the data output buffer, a timing at which data is actually outputted from the data output buffer can be made closer to the time point t
1
.
On the other hand, as one of general operating conditions for a synchronous semiconductor memory device, a word organization indicating the number of bits of data communicated with the outside in a one time data input/output operation is set. In the present specification, a setting of a word organization in which N bit data N is a natural number) is communicated in a one time data input/output operation is expressed by “×N” hereinafter.
In
FIG. 13
, shown is a case where the replica delay time Tdr in the DLL circuit is set so as to be equal to a buffer processing time Tdb (×4) in a case of a word organization ×4. In this case, an access time tAC when a word organization is ×4 can be set to tAC=0.
As shown in
FIG. 13
, however, if a setting of the word organization is altered and the number of bits communicated in a one time data input/output operation increases, a processing time in the output buffer increases. That is, when the word organization is set to ×8 and ×16 in two ways, processing times Tdb (×8) and Tdb (×16) become longer than a processing time Tdb (×4) in a case of a word organization ×4 by &Dgr;Tdb
1
and &Dgr;Tdb
2
, respectively.
This is because as the number of bits of data outputted in one time increases, a tendency arises that an operating current of the data output buffer increases and with the increase in the operating current, an operating power source voltage of the data output buffer falls.
On the other hand, in a prior art DLL circuit, it has been common that the replica delay time is set to a fi×ed value; therefore, there was a problem since an access time varies if an operating condition represented by a word organization alters.
That is, as shown in
FIG. 13
, if a replica delay time Tdr in the DLL circuit is adjusted in correspondence to a case of a word organization ×4, there has arisen a problem that changes in the processing time &Dgr;Tdb
1
and &Dgr;Tdb
2
show up as changes in the access time tAC, as they are, without being compensated in a case where word organizations are set ×8 and ×16, respectively.
In general, setting of the word organization is performed by wire bonding in an assembly step; therefore, a prior art configuration in which a replica delay time Tdr in a DLL circuit is fixed in a fabrication process of a chip has had difficulty securing an proper access time while securing a degree of freedom in setting of the word organization.
On the other hand, a configuration is also conceived in which stability of an operating power source voltage of a data output buffer is raised such that a processing time in the data output buffer does not alter even if the word organization is altered. In this case, however, stabilization capacitor with large capacitance is required to be provided to the operating power source voltage, which places a burden on a layout design.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide a configuration of a synchronous semiconductor memory device capable of performing data output at a proper timing-according to setting of an operating state represented by a word organization.
The present invention will be summarized as follows: The present invention is a synchronous semiconductor memory device operating in synchronization with an external clock and includes: a data output buffer circuit; and a control clock generating circuit. The data output buffer circuit performs an output operation of read data to the outside, requiring a processing time corresponding to an operating condition. The control clock generating circuit generates a control clock activating an output operation of the data output buffer circuit according to an external clock. The control clock generating circuit includes: a delay circuit for delaying the external clock to generate the control clock; a delay control section controlling a delay time in the delay circuit according to a phase difference between the external clock and a feedback clock; and a replica delay time adjusting section, provided between the delay circuit and the delay control circuit, and for delaying the control clock by a replica delay time corresponding to the processing time to generate the feedback clock. The replica delay time adjusting section adjusts the replica delay time according to an operating condition.
Therefore, a main advantageous point of the present invention is that an operating timing of the data output buffer circuit can be set, reflecting a change in the processing time of the data output buffer circuit corresponding to an operating condition. As a result, a data output timing can be prop

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