Synchronous semiconductor memory device of fast random cycle...

Details Synchronous semiconductor memory device of fast random cycle... Synchronous semiconductor memory device of fast random cycle...

2006-06-20

2006-06-20

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S189080, C365S194000, C365S195000, C365S196000, C365S201000, C365S233100, C365S233500

Reexamination Certificate

active

07064988

ABSTRACT:
An FCRAM includes first to third circuits. The first circuit generates a first signal based on a command detection signal. The second circuit is configured to receive the command detection signal, an operation mode specifying signal and a selection signal and generate a second signal which causes the start timing of the operation of a row-system circuit to be synchronized with the input timing of a second command. The third circuit is configured to select the first signal when a normal operation mode is specified by the operation mode specifying signal, select the second signal when a test mode is specified, and generate a third signal used to activate at least part of the memory cells in a memory cell array based on a selected one of the first and second signals and the selection signal.

REFERENCES:
patent: 6426915 (2002-07-01), Ohshima et al.
patent: 6563760 (2003-05-01), Song
patent: 6882586 (2005-04-01), Sato et al.
patent: 6885606 (2005-04-01), Kumazaki et al.
patent: 2003/0102885 (2003-06-01), Tsuboi et al.
patent: 2003/0226064 (2003-12-01), Nakazawa
patent: 2004/0165452 (2004-08-01), Nakano

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