Synchronous semiconductor memory device in which burst counter i

Details Synchronous semiconductor memory device in which burst counter i Synchronous semiconductor memory device in which burst counter i

1996-12-17

1999-04-13

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

365236, 36518905, G06F 1200

Patent

active

058939253

ABSTRACT:
A read control flip-flop circuit is activated upon activation of an internal readout instruction signal from a command decoder to generate a signal for activating an internal data reading circuit. A write control flip-flop circuit activates an internal data writing circuit in response to an internal write operation instruction signal from the command decoder. When one of the internal write instruction signal and the internal readout instruction signal from this command decoder is activated, a burst length counter counts a predetermined number of clock cycles, and when the counted value reaches a predetermined value, a reset signal is activated to reset the read control flip-flop circuit and the write control flip-flop circuit. Thus, the layout area of the control portion for internal data read operation and internal data write operation in a synchronous semiconductor memory device is reduced.

REFERENCES:
patent: 5269015 (1993-12-01), Shires
patent: 5386385 (1995-01-01), Stephens
patent: 5566108 (1996-10-01), Kitamura
patent: 5568445 (1996-10-01), Park
DRAM 1993 Data Book, from Micron Semiconductor, Inc. Author unknown, pp. 2-1, 2-2, and 2-3, Mar. 1993.

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