Synchronous semiconductor memory device having set up time of ex

Details Synchronous semiconductor memory device having set up time of ex Synchronous semiconductor memory device having set up time of ex

1998-12-16

2000-02-15

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Bad bit

36523008, 365233, G11C 700, G11C 800

Patent

active

06026036&

ABSTRACT:
In a synchronous semiconductor memory device, a predecoder is provided between a former stage address input register formed of first latch circuits and a latter stage address input register formed of second latch circuits. The first and second latch circuits operate in response to first and second internal clock signals complementary to each other. A predecode signal can be latched by the second latch circuit even when the generation of the predecode signal is not in time for the rise of the second internal dock signal due to delay of the input of an external address signal. Accordingly, the set up time for the external address signal can be reduced.

REFERENCES:
patent: 5086414 (1992-02-01), Nambu et al.
patent: 5687125 (1997-11-01), Kikuchi
patent: 5841711 (1998-11-01), Watanabe
patent: 5862097 (1999-01-01), Toda
patent: 5930183 (1999-07-01), Kojima et al.

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