Synchronous semiconductor memory device having redundant circuit

Details Synchronous semiconductor memory device having redundant circuit Synchronous semiconductor memory device having redundant circuit

1998-11-18

2000-05-23

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

36523003, G11C 700, G11C 800

Patent

active

060672609

ABSTRACT:
A redundant memory cell column region provided corresponding to respective regular memory cell column regions can have data read and written through a sub I/O line pair and a main I/O line pair independent to those of the regular memory cell column region. Also, one redundant memory cell column region can be connected to a corresponding global I/O line pair G-I/O of any of the regular memory cell column regions via a multiplexer to be replaceable of any of two regular memory cell column regions.

REFERENCES:
patent: 5386387 (1995-01-01), Tanizaki
patent: 5544113 (1996-08-01), Kirihata et al.
patent: 5652725 (1997-07-01), Suma et al.
patent: 5708612 (1998-01-01), Abe
patent: 5761138 (1998-06-01), Lee et al.
"A Flexible Redundancy Technique for High-Density DRAM's", M. Horiguchi, et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 1, Jan. 1991, pp. 12-17.
"Fault-Tolerant Designs for 256 Mb DRAM", T. Kirihata, et al., IEEE Journal of Solid-State Circuits, vol. 31, No. 4, Apr. 1996, pp. 558-565.

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