Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-02-11
2001-12-18
Zarabian, Amir (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230030
Reexamination Certificate
active
06331956
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to synchronous semiconductor memory devices, and more particularly, to the structure of a redundant circuit in a synchronous semiconductor memory device.
2. Description of the Background Art
In order to comply with the higher operation speed of recent microprocessors (referred to as MPU hereinafter), a synchronous DRAM (referred to as SDRAM hereinafter) is used that operates in synchronization with a clock signal to realize high speed access of a dynamic random access memory (referred to as DRAM hereinafter) employed as a main storage device. Control of the internal operation of such SDRAMs is carried out with the row related operation and the column related operation separated from each other.
In order to further increase the operation speed in a SDRAM, a bank structure is employed in which the memory cell array is divided into a plurality of banks that can operate independent of each other. In other words, the row related operation and the column related operation are controlled independently for each bank.
Each of such banks is often divided into blocks called a memory cell array mat in which are provided a sense amplifier and the like to amplify data from a selected memory cell via a bit line pair.
In order to improve the fabrication yield and the like of the SDRAM having the above structure, the so-called redundancy replacement is generally canited out where a memory cell row or memory cell column including defection is replaced with a redundant row or column that is prepared in advance.
This redundancy replacement is generally carried out on the basis of the range of the memory cell array mat where the above-described operation is activated.
In this case, the range of memory cells that can be replaced with one redundant row (or one redundant column) will be limited to this memory cell array mat range. There is a problem that the area penalty is increased by incorporating any extra redundant row (column), or that the repair efficiency by redundancy replacement is reduced.
In a SDRAM that must carry out operation at high speed, there was a problem that a sufficient operational margin could not be obtained when redundancy replacement is carried out since extra time is necessary to determine whether or not to effect redundancy replacement with respect to an externally applied address signal.
There was also a problem that the operating current and power consumption during standby are increased in accordance with a larger storage capacity of the memory.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a synchronous semiconductor memory device integrated in high complexity having a redundancy replace circuit of high repair efficiency and that allows increase in the chip area to be suppressed.
Another object of the present invention is to provide a synchronous semiconductor memory device that has a sufficient operational margin and that can speed up the access time even when redundancy replacement is carried out.
A further object of the present invention is to provide a synchronous semiconductor memory device that allows increase in power consumption suppressed even when redundancy replacement is carried out.
According to an aspect of the present invention, a synchronous semiconductor memory device receiving an externally applied address signal and control signal in synchronization with an external clock signal includes a memory cell array, an address bus, a plurality of first column select circuits, a plurality of second column select circuits, a plurality of first input/output line pairs, and a plurality of second input/output line pairs.
The memory cell array has a plurality of memory cells arranged in a matrix. The memory cell array includes a plurality of regular memory cell blocks, and a plurality of redundant memory cell blocks provided corresponding to every first plurality of regular memory cell blocks to replace a defective memory cell in a corresponding first plurality of regular memory cell blocks.
The address bus is provided common to the plurality of regular memory cell blocks and redundant memory cell blocks to transmit an address signal.
The plurality of first column select circuits are provided corresponding to the regular memory cell blocks to select a memory cell column in a corresponding regular memory cell block according to an address signal through the address bus. The plurality of second column select circuits are provided corresponding to the redundant memory cell blocks to select a memory cell column in a corresponding redundant memory cell block according to an address signal from the address bus.
The plurality of first input/output line pairs are provided corresponding to the regular memory cell blocks to transmit data read out from a selected memory cell of a corresponding regular memory cell block. The plurality of second input/output line pairs are provided corresponding to the redundant memory cell blocks to transmit data read out from a selected memory cell of a corresponding redundant memory cell block.
The first and second column select circuits are activated in response to selection of a corresponding memory cell block according to an address signal.
Preferably, the first input/output line pair includes a second plurality of first sub input/output line pairs, and a plurality of first main input/output line pairs. The second input/output line pair includes a second plurality of second sub input/output line pairs and a plurality of second main input/output line pairs. The synchronous semiconductor memory device includes a plurality of first subamplifier circuits, a plurality of second subamplifier circuits, a plurality of subamplifier control signal lines, and a subamplifier activation circuit.
The second plurality of first sub input/output line pairs are provided in a row direction of the memory cell array. The plurality of first main input/output line pairs are provided in a column direction of the memory cell array.
The second plurality of second sub input/output line pairs are provided in the row direction of the memory cell array. The plurality of second main input/output line pairs are provided in the column direction of the memory cell array.
The plurality of first subamplifier circuits are provided corresponding to respective crossings of a first sub input/output line pair and a first main input/output line pair. The plurality of second subamplifier circuits are provided corresponding to respective crossings of a second sub input/output line pair and a second main input/output line pair.
The plurality of subamplifier control signal lines are provided common to the first subamplifier circuit and the second subamplifier circuit in the row direction of the memory cell array to transmit a subamplifier select signal.
The subamplifier activation circuit renders the second subamplifier circuit active in response to replacement being carried out of a memory cell in the regular memory cell array block with a memory cell in a redundant memory cell block.
Alternatively, the first input/output line pair preferably includes a second plurality of first sub input/output line pairs, and a plurality of first main input/output line pairs. The second input/output line pair includes a second plurality of second sub input/output line pairs and a plurality of second main input/output line pairs. The synchronous semiconductor memory device includes a plurality of first main amplifier circuits, a plurality of second main amplifier circuits, a data bus, and a multiplexer circuit.
The second plurality of first sub input/output line pairs are provided in the row direction of the memory cell array. The plurality of first main input/output line pairs are provided in the column direction of the memory cell array.
The second plurality of second sub input/output line pairs are provided in the row direction of the memory cell array. The plurality of second main input/output line pairs are provided in the column direction of the memory cell array.
The plurality o
Ooishi Tsukasa
Shimano Hiroki
Tomishima Shigeki
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Phung Anh
Zarabian Amir
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