Synchronous semiconductor memory device having a...

Details Synchronous semiconductor memory device having a... Synchronous semiconductor memory device having a...

2005-03-15

2005-03-15

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189011

Reexamination Certificate

active

06868020

ABSTRACT:
A synchronous DRAM has a test mode wherein a specified external signal is input to a command decoder of the DRAM. The command decoder generates a plurality of internal commands including activating signal for selecting a word line, write signal, precharge signal, another activating signal and read signal at consecutive timings which do not depend on an external clock signal. A low-speed memory tester can be used for testing the high-speed synchronous DRAM.

REFERENCES:
patent: 6385104 (2002-05-01), Koshikawa
patent: 6385125 (2002-05-01), Ooishi et al.
patent: 6536004 (2003-03-01), Pierce et al.
patent: 11-144497 (1999-05-01), None
patent: 11-306797 (1999-11-01), None

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