Synchronous semiconductor memory device capable of high speed re

Static information storage and retrieval – Addressing – Sync/clocking

Patent

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Details

365200, 365222, 36523008, G11C 800

Patent

active

061341797

ABSTRACT:
An address input is received earlier than data input, and a result of decoding of a column address at the time of writing and results of substitution determination for a redundancy memory column are held in a latch circuit corresponding to each bank. When the data arrives at the bank, the data is immediately written to each bank, utilizing the results of address processing. Operation frequency of the chip is not limited by the conventionally experienced wasteful wait time for the data in the process of writing, and efficient data input/output is possible.

REFERENCES:
patent: 5673233 (1997-09-01), Wright et al.
patent: 5923595 (1999-07-01), Kim
patent: 5926434 (1999-07-01), Mori
patent: 5982697 (1999-11-01), William et al.

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