Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-07-19
2003-09-09
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S233100
Reexamination Certificate
active
06618310
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a refresh operation in a synchronous semiconductor memory device, and more particularly to a synchronous semiconductor memory device, enabling reduction of current consumption in a self-refresh operation.
2. Description of Related Art
With the recent development in computer technology which realizes animations and other advanced features, there is a growing demand for increasing the capacity and speed of semiconductor memory devices represented by a dynamic random access memory (DRAM). To meet this demand, synchronous semiconductor memory devices, represented by a large-capacity synchronous DRAM, have been developed. On the other hand, this demand necessarily results in an increase in current consumption in a circuit operation, so that it is desired to reduce current consumption in a synchronous semiconductor memory device.
Particularly, a refresh operation of memory cells in a memory device such as a synchronous DRAM needs to be performed in a predetermined cycle. Therefore, current consumption in a refresh operation have been reduced by setting the refresh cycle long in accordance with the actual performance value of charge retention time determined based on charge retention characteristics.
In addition, since a synchronous semiconductor memory device operates in synchronization with an external basic clock, device temperature rises as operating current is increased due to an increase in the speed of the external basic clock. Because charge retention characteristics of memory cells largely depend on the device temperature, charge retention time is decreased as the temperature rises. Therefore, it is necessary to shorten the refresh cycle in a high temperature range, and to set the refresh cycle suitable for the device temperature which changes according to the frequency of the external basic clock.
With regard to conventional arts, for example, the Japanese Laid-Open Patent Publication No.5-217369 describes a refresh timer that outputs a refresh signal in a semiconductor memory device requiring a refresh operation of memory cells, comprising oscillation circuit for outputting an oscillation signal of predetermined frequency, frequency division circuit for dividing frequency of the oscillation signal, and adjustment circuit for adjusting the frequency division cycle of the frequency division circuit to the value suitable as the refresh cycle of the memory cells.
In the aforementioned refresh timer in the semiconductor memory device, the refresh cycle can be adjusted to the accurate refresh cycle required for each device after production, even when oscillation circuit with relatively poor accuracy is used.
The Japanese Laid-Open Patent Publication No.5-307883 discloses an oscillator circuit, comprising inverter circuits between a high-potential power line and a low-potential power line in which predetermined number of PMOS transistors and NMOS transistors are connected in series; first resistance circuit between the high-potential power line and the low-potential power line in which a first PMOS transistor for inputting to gates the potential level of the low-potential power source line and a resistor are sequentially connected in series, and a contact between the first PMOS transistor and the resistor is a low-potential output end; and second resistance circuit between the high-potential power source line and the low-potential power line in which a resistor and a first NMOS transistor for inputting to gates the potential level of the high-potential power source line are sequentially connected in series, and a contact between the resistor and the first NMOS transistor is an high-potential output end, wherein the low-potential output end of the first resistance circuit is connected with the gates of the PMOS transistors in the inverter circuits proximate to the high-potential power source line, and the high-potential output end of the second resistance circuit is connected with the gates of the NMOS transistors in the inverter circuits proximate to the low-potential power source line, and the inverter circuits are multi-stage connected in a loop-shape to generate a predetermined clock cycle.
Since the charge retention time of memory cells in a semiconductor memory device is decreased as the device temperature rises, the temperature characteristics of the refresh cycle should be set to have a negative correlation to the device temperature in order to retain charge. In view of this, in the aforementioned oscillator circuit, the temperature characteristics of the oscillation cycle are set to have the negative correlation to the device temperature just as the temperature characteristics of the refresh cycle for retaining charge, and thus the refresh cycle is shortened as the device temperature rises. In this way, the reliability with which the memory cells retain charge at high temperatures is enhanced. In addition, since the refresh cycle can be set long at normal working temperatures, the operating current for a refresh operation can be prevented from increasing. Accordingly, current consumption can be reduced.
Furthermore, the Japanese Laid-Open Patent Publication No.7-73668 describes a self-refresh cycle adjustment circuit in a semiconductor memory device which generates a master clock signal for setting the refresh cycle in a semiconductor memory device. This self-refresh cycle adjustment circuit comprises pulse train generation circuit for generating pulse trains in a predetermined cycle according to the refresh mode set by an external control signal, and dividing frequency of the pulse trains sequentially to output a number of frequency-divided pulse trains each of which has a different cycle; at least one temperature detection circuit for detecting change in surrounding temperature based on the internally-set standard level to output a temperature detection signal; and master clock generation circuit for selecting one of the frequency-divided pulse trains according to the temperature detection signal and outputting a master clock signal based on the selected frequency-divided pulse train.
In the aforementioned self-refresh cycle adjustment circuit, the self-refresh cycle can be actively adjusted according to change in surrounding temperature. Furthermore, the self-refresh cycle can be automatically adjusted so as to be adapted to various operating environments.
In the refresh timer described in the Japanese Laid-Open Patent Publication No.5-217369, the refresh cycle can be accurately adjusted to the refresh cycle required for each semiconductor memory device after production, even when oscillation circuit with relatively poor accuracy is used.
However, this adjustment needs to be made to each semiconductor memory device using adjustment circuit such as a trimming circuit, and the optimum refresh cycle cannot be determined without measuring variations in characteristics of each device due to production variations. Since characteristics to be measured include temperature characteristics, much test time is required to measure characteristics before adjustment, resulting in a problem that productivity of semiconductor devices cannot be improved.
Furthermore, when the refresh cycle is adjusted using adjustment circuit such as a trimming circuit, a refresh operation is always performed in a constant cycle. Since this cycle needs to be set such that the memory cells can retain charge even under the most extreme conditions (for example, when power supply voltage is low, or temperature is high), a refresh operation is performed in a cycle shorter than that required based on charge retention characteristics of the memory cells under normal use conditions. This causes the problem that current consumption in a refresh operation becomes greater than necessary.
In the oscillator circuit disclosed in the Japanese Laid-Open Patent Publication No.5-307883, the self-refresh cycle is shortened as temperature rises to enhance the reliability with which the memory cells retain charge at high temperatures. At the sam
Higashiho Mitsuhiro
Sato Hajime
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Ho Hoai
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