Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2001-08-30
2002-10-15
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Signals
C365S191000, C365S233100, C365S189050, C365S230080, C365S189080, C365S230030, C365S227000
Reexamination Certificate
active
06466492
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a synchronous semiconductor memory device and a method for controlling an input circuit of a synchronous semiconductor memory device. More particularly, the present invention pertains to the reduction of power consumption in a synchronous semiconductor memory device.
Due to the increase in the processing speed of processors, recent semiconductor memory devices, such as a synchronous DRAM (SDRAM), have data input terminals that correspond to 32 or 64 bit data. To transfer data to and from a processor, the SDRAM first receives an active command from the processor in correspondence with a synchronizing signal (CLK). When several cycles of the synchronizing signal elapses from when the SDRAM is activated, the processor provides the SDRAM with a command such as that for reading or writing data. In response to the command, the SDRAM transfers data to or from the processor.
The latency is set during a write mode during which data is written to the SDRAM. When the latency is “0” in the write mode, the time for receiving a write command is substantially the same as the time for receiving write data (Data-In; DIN). In other words, the SDRAM receives the write command and the write data in response to the same synchronizing signal (CLK).
As the speed of the device increases, if the SDRAM starts to accept the write data (activation of input circuit) after receiving the write command, the SDRAM may not be able to receive the write data at a predetermined time. Thus, the SDRAM must be capable of simultaneously receiving the write command and the write data.
When the SDRAM is capable of receiving a write command, the SDRAM is also capable of receiving a read command and other commands. A plurality of data input circuits must always be activated to enable the input of write data whenever receiving the write command even though the SDRAM receives other commands. Thus, when the SDRAM is in a state capable of receiving each command, current flows through the input circuits even if data is actually not written. This consumes current.
FIG. 1
shows a schematic view illustrating the shifting of states in the SDRAM.
The SDRAM has a plurality of memory banks (hereafter simply referred to as banks). The SDRAM shifts from a bank active state to other states, such as a precharge state, a bank active suspend state, a read state, or a write state. The bank forms a memory unit that may be accessed in parallel. For example, an SDRAM having two banks includes two row address input systems of a typical DRAM. This enables an A bank and a B bank of the SDRAM to independently receive active commands.
FIG. 1
illustrates the shifting of states in a single bank. The arrows drawn by solid lines represent shifting performed by command inputs (manual inputs), and the arrows drawn by broken lines represent automatic shifting (automatic sequence).
The SDRAM shifts from the bank active state to a bank active suspend state, a precharge state, a write state, or a read state in a single cycle of the synchronizing signal (CLK).
Input circuits connected to terminals, which receive commands and address signals, are activated to shift the state of the SDRAM. Further, data input circuits, which are connected to data input terminals, are each activated to shift the SDRAM to the write state.
FIG. 2
is a schematic block diagram of a first example of a prior art SDRAM
10
.
The SDRAM
10
includes a clock buffer
1
, a flip-flop (SFF)
2
, an input buffer
3
, a read/write (I/O) control circuit
4
, an input buffer
5
, and an output buffer
6
.
The clock buffer
1
receives and amplifies a clock signal CLK to generate an internal clock signal CLK
1
. The internal clock signal CLK
1
is provided to the SFF
2
. The input buffer
3
receives a mask control signal DQM. The input buffer
3
amplifies the mask control signal DQM and generates an internal mask control signal DQM
1
. The internal mask control signal DQM
1
is provided to the SFF
2
. The SFF
2
latches the internal mask control signal DQM
1
in synchronism with the internal clock signal CLK
1
and provides the I/O control circuit
4
with the latched mask control signal DQM
1
as a synchronous mask control signal DQMS.
Referring to
FIG. 3
, the input buffer
5
includes an AND circuit
5
a
that receives input data DQ and a bank active recognition signal BACT. The input buffer
5
amplifies the input data DQ when the recognition signal BACT is active and generates write data Din. The write data Din is provided to the I/O control circuit
4
.
The I/O control circuit
4
provides the output buffer
6
with read data Dout, which is read from a bank (not shown). The output buffer
6
amplifies the read data Dout and generates output data DQ.
Accordingly, if the bank active recognition signal BACT is inactive and the SDRAM
19
is in an idle state, a refreshing state, or a power down state, the input buffer
5
is disabled. This decreases power consumption. However, if the recognition signal BACT is active, power consumption does not decrease.
FIG. 4
is a schematic circuit diagram of a power cut circuit
50
, which decreases power consumption in an SDRAM.
The power cut circuit
50
is arranged in the SDRAM to receive a plurality of control signals generated by internal circuits (not shown). The control signals include an A bank RAS enable signal ARAE, a B bank RAS enable signal BRAE, a reading signal READB, an output enable mask signal OEMSK, and a power down signal PWDNB.
The reading signal READB goes low for a clock cycle, which has a predetermined burst length, from when a read command is provided during a read mode. The output enable mask signal OEMSK masks (prohibits use of) an internal enable signal in the read mode. The mask signal OEMSK shifts based on a data mask signal DQM.
The power down signal PWDNB shifts the SDRAM to the power down mode based on a clock enable signal CKE. A power down signal PWDNB
2
for a first stage input circuit is low in the power down mode.
The power cut circuit
50
includes a first OR circuit
11
, a second OR circuit
12
, a NAND circuit
13
, and an inverter circuit
14
. The first OR circuit
11
receives the A bank RAS enable signal ARAE and the B bank RAS enable signal BRAE. The second OR circuit
12
receives the reading signal READB and the output enable mask signal OEMSK.
The NAND circuit
13
receives an output signal of the first OR circuit
11
, an output signal of the second OR circuit, and a power down signal PWDNB. The inverter circuit
14
inverts the output signal of the NAND circuit
13
and generates the first stage input circuit power down signal PWDNB
2
.
The operation of the power cut circuit
50
will now be discussed with reference to FIG.
5
.
When the power cut circuit
50
receives an A bank active command in cycle T
1
of the clock signal CLK, the A bank RAS enable signal ARAE goes high. Then, when the power cut circuit
50
receives the A bank read command in cycle T
2
of the power cut circuit
50
, the reading signal READB goes low. The output enable mask signal OEMSK is normally low. Thus, the first stage input circuit power down signal PWDNB
2
goes low, and the first stage input circuit undergoes a power cut during a read operation.
When the output enable mask signal OEMSK goes high, the power down signal PWDNB goes high and the first stage input circuit is activated. The mask signal OEMSK is generated after the data mask signal DQM goes high. Accordingly, operation of the first stage input circuit is enabled again in cycle T
5
and activated before cycle T
6
starts. When a write command is input during cycle T
7
, input write data, which is input synchronously with the write command, is acquired.
The A bank write command is input during cycle T
7
to prevent bus fights of read/write data (confrontation between output signal Q
3
and input signal D
1
) outside the SDRAM.
The time during which the SDRAM is in an idle state, a refreshing state, a power down state, or a bank active state takes up a large portion of the entire SDRAM operation t
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Tran Andrew Q.
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