Synchronous semiconductor memory device

Details Synchronous semiconductor memory device Synchronous semiconductor memory device

2002-09-17

2004-05-04

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233100, C365S236000

Reexamination Certificate

active

06731559

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-284111, filed Sep. 18, 2001; and No. 2002-251604, filed Aug. 29, 2002, the entire contents of both of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a synchronous semiconductor memory device. More specifically, this invention relates to a high-speed random-cycle synchronous semiconductor memory (FCRAM) which has the function of reading and writing data from and into the memory cell array at random at high speeds and which is used in, for example, a high-speed-cycle synchronous FCRAM (SDR-FCRAM) or a double-data-rate synchronous FCRAM (DDR-FCRAM) that realizes twice the data transfer rate of an SDR-FCRAM.
2. Description of the Related Art
Conventional synchronous DRAMs (SDRAMs) are such that they make the data access speed of DRAMs (dynamic random-access memories) as fast as SRAMs (static random-access memories) and enable a greater data bandwidth (the number of data bytes per unit time) at a higher clock frequency. SDRAMs have been put to practical use since the 4-Mbit/16-Mbit DRAM generations. In the 64-Mbit DRAM generation, most of the DRAMs now in use are SDRAMs.
Recently, an attempt has been made to make the data transfer rate of SDRAMs much faster. For example, double-data-rate SDRAMs (DDR-SDRAMs) that operate at a data transfer rate twice that of conventional equivalents have been proposed and are now being commercialized.
Although being faster in the data transfer rate, or being improved in the bandwidth, SDRAMs have the following problem: it is difficult to access the cell data in the memory core at higher speed. The reason for this is that, in the case of SDRAMs, the data access from a different row address as a result of the change of the row access requires a destructive read operation unique to DRAMs and an amplify operation and that it also requires a specific length of time (or core latency) for a precharge operation preceding the next core access. Therefore, it is difficult to radically speed up the core cycle time (or random cycle time tRC).
To solve this problem, a Fast Cycle RAM (FCRAM) has been proposed which performs a core access operation and a precharge operation in a pipeline manner, thereby decreasing the random cycle time tRC to less than ½ that of a conventional SDRAM (for example, see “a 20-ns Random Access Pipelined Operation DRAM,” VLSI Symp. 1998). In recent years, products using such an FCRAM are going to be commercialized in the field of networks that transfer random data at high speeds, centering on LAN switches and routers, which have used SRAMs up to now.
Here, the command system including the basic operations of FCRAMs will be explained briefly (for further details, see, for example, Japanese Patent Application No. 11-373531 (Jpn. Pat. Appln. KOKAI Publication No. 2001-189077).
FIG. 8
shows how the state of FCRAM changes according to a command input. In
FIG. 8
, the way the command input is determined by a combination of a first command and a second command is illustrated.
FIGS. 9A and 9B
show the relationship between the commands in FIG.
8
and pin inputs corresponding to the commands (in function tables).
In the FCRAM, two pins, a chip select (/CS) pin and a function control (FN=row address strobe/RAS) pin, are generally located as external terminals for inputting commands for controlling internal circuit operations. It is impossible to determine many command inputs by using only the two pins. To overcome this problem, combining a first command and a second command enables a plurality of commands to be determined by only the two pins, the /CS pin and the FN pin.
In
FIG. 8
, a write active command WRA (Write with Auto-close) and a read active command RDA (Read with Auto-close) are first commands. A lower address latch command LAL (Lower Address Latch), a mode register set command MRS (Mode Register Set), and an auto refresh command REF (Auto Refresh) are second commands.
As shown in
FIG. 9A
, as for the first commands, when the input level of the /CS pin is low and the input level of the FN pin is high, a read active command RDA is set as a command input. In addition, when the input level of the /CS pin is low and the input level of the FN pin is low, a write active command WRA is set as a command input. As shown in
FIG. 9B
, as for second commands, when the input level of the /CS pin is high, a lower address latch command LAL is set as a command input. Moreover, when the input level of the /CS pin is low, a mode register set command MRS and an auto refresh command REF are set as command inputs.
Specifically, as shown in
FIG. 8
, when each of a first command and a second command is inputted in the wait state (STANDBY), a read active command RDA or a write active command WRA is given directly. In this case, as seen from the tables shown in
FIGS. 9A and 9B
, the input of a command is accepted when the input level of the /CS pin is made low. The distinction between a read command and a write command is made according to the level of the input supplied to the FN pin. In this example, if the command is a read command, the FN pin is set high. If the command is a write command, the FN pin is set low.
Furthermore, a first command can be used to give a row address for sense amplifier division decoding. There is a limit to the number of pins of a package. Thus, some of the existing control pins are used as address pins, thereby suppressing an increase in the number of pins.
FIG. 10
shows the pin allocation of a double-data-rate synchronous FCRAM (DDR-FCRAM) package some of whose control pins are used as address pins, as compared with the pin allocation of a DDR-SDRAM package. Explanation will be given, taking a 66-pin TSOP (Thin Small Outline Package) standardized in JEDEC (Joint Electron Devices Engineering Council) as an example.
In the FCRAM in this example, the column address strobe (/CAS) pin and write enable (/WE) pin of the SDRAM are converted into address pins A
13
, A
14
. This increases the number of sense amplifiers to be decoded, preventing the number of sense amplifiers to be activated from being limited.
An address taken in by a first command is called an upper address UA and an address taken in by a second command is called a lower address LA.
With the rising edge of a clock in a first command, the upper address UA is taken in from the address pins A
13
, A
14
corresponding to the /WE pin and /CAS pin and normal address pins A
0
to A
12
. If the first command is a read command, a word line WL is selected according to the row address. Then, the data from the memory cell MC connected to the selected word line WL is read onto a bit line pair BLn, /BLn. The read-out data is amplified by a bit-line sense amplifier S/A. The input of the first command completes the operations up to this point. In
FIG. 10
, the /WE pin and /CAS pin change in level according to the input of addresses. Moreover, the /RAS pin is changed in level according to the FN input.
Next, after one clock cycle since the first command was inputted, any one of a lower address latch command LAL, a mode register set command MRS, and an auto refresh command REF is inputted as a second command.
The following is an explanation of a case where, in the second command, the /CS pin is set high (command LAL) and column addresses CA
0
to CAj (lower addresses LA) are taken in from address pins A
0
to A
14
. In this case, a column address is only taken in as the second command. That is, the column select line CSL corresponding to the column address is selected. In this way, the data amplified by the bit-line sense amplifier S/A is transferred to a data-line pair MDQ. Then, the data is amplified again by a read buffer (or secondary sense amplifier) DQRB. Finally, the data is outputted at an output pin.
A command decoder for realizing the aforementioned operations is composed of, for example, a controller, a first-command decode

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