Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate
1999-07-19
2003-12-23
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
Reexamination Certificate
active
06668345
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device, and particularly to a structure of data writing related circuitry of a synchronous semiconductor memory device.
2. Description of the Background Art
In accordance with increase in the operating speed of recent microprocessors (referred to as MPU hereinafter), a synchronous DRAM that operates in synchronization with a clock signal and the like (synchronous DRAM: referred to as SDRAM hereinafter) are used to realize high speed access of dynamic random access memories (referred to as DRAM hereinafter) employed as the main storage device.
The internal operation of such SDRAMs is divided into the row related operation and column related operation for control.
To allow further increase in the operation speed in a SDRAM, a bank structure is employed where memory cell arrays are divided into a plurality of banks that are operable independently. In other words, the operation of each bank is under independent control for a row related operation and a column related operation.
The above bank is often divided into blocks that are termed a memory cell array mat in which is provided a sense amplifier and the like to amplify data from a selected memory cell through a pair of bit lines.
In an SDRAM having such a structure, so-called redundancy replacement is carried out to replace a memory cell row or memory cell column in which a defect is included with a redundant row or redundant column that is provided in advance for the purpose of improving the fabrication yield and the like.
This redundancy replacement is generally carried out for every memory cell array mat range that is rendered active by the above operation.
In this case, the range of memory cells that can be replaced with one redundant row (or one redundant column) will be restricted to the range of the memory cell array mat. There was a problem that the area penalty is increased by incorporating extra redundant rows (columns), or that the repair efficiency by redundancy replacement is degraded.
When redundancy replacement is carried out in a SDRAM that requires high speed operation, there is a problem that a sufficient operation margin cannot be achieved since extra time for the process of determining whether to effect redundancy replacement or not with respect to an externally applied address signal is required.
Furthermore, a conventional synchronous semiconductor memory device imposes problems set forth in the following.
FIG. 71
is a schematic block diagram showing a structure of a conventional redundancy determination circuit
6900
. Redundancy determination circuit
6900
includes a plurality of address storage unit pairs
6902
a
,
6902
b
-
6916
a
,
9616
b
provided between a common node nc and a ground potential, a p channel MOS transistor
6920
connected between common node nc and a power supply potential Vcc, rendered conductive in response to activation (L level) of a precharge signal PR, an inverter
6924
provided between common node nc and an output node nr, and a p channel MOS transistor
6922
provided between power supply potential Vcc and common node nc, and receiving the output of inverter
6924
at its gate.
Among address storage units
6902
a
-
6916
b
, respective pairs of address storage units, for example address storage unit
9602
a
and address storage unit
9602
b
, are formed to receive internal address signals int.Add
0
and /int.Add
0
complementary to each other. The other pairs of address storage units also receive complementary internal address signals corresponding to different bits of the internal address.
FIG. 72
is a circuit diagram showing a structure of address storage unit
9602
a
of FIG.
71
.
Address storage unit
9602
a
includes a fuse element
9630
and an n channel MOS transistor
9632
connected in series between common node nc and ground potential GND. The gate of n channel MOS transistor
9632
receives internal address signal int.Add
0
.
In the case where common node nc is precharged and output node nr attains the L level by activation of, for example, precharge signal PR, common node nc is discharged through any of the address storage units so that output node nr is driven into an H level when none of address storage units
9602
a
-
9616
b
have the fuse element blown out.
In the case where any of address storage units
9602
a
-
9616
b
has fuse element
9630
blown out, common node nc is not discharged if the programmed address matches internal address signal int.Add.
Therefore, a defective address (address of defective cell) according to a defective bit can be stored in a non-volatile manner by blowing out fuse element
9630
in advance.
Here, fuse element
9630
includes an element such as an AC wire or polysilicon wire that is burned out by laser blow.
As the number of bits of the address signal is increased in accordance with a larger memory capacity of a synchronous semiconductor memory device, the number of address storage units connected to common node nc will also increase. As a result, the parasitic capacitance of common node nc is increased. This means that the time until a signal of a comparison result is output becomes longer.
Thus, there was a problem that the time for redundancy determination becomes longer in response to a greater memory capacity, which in turn causes a longer access time.
There is a case where data writing must be selectively inhibited for data corresponding to a predetermined period and a predetermined data input/output terminal in storing image data in a synchronous semiconductor memory device. There was a problem that the speed of writing data will be limited if there is a skew between the data designating inhibition of data writing and the data to be written.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a synchronous semiconductor memory device that has high repair efficiency and that can speed the access time when redundancy replacement is carried out even in a synchronous semiconductor memory device that is integrated in high circuit complexity.
Another object of the present invention is to provide a synchronous semiconductor memory device that can suppress increase in the time required for a writing operation even in the operation of selectively inhibiting data writing.
According to an aspect of the present invention, a synchronous semiconductor memory device receiving an address signal of a plurality of bits in synchronization with an external clock signal includes a memory cell array, and a memory cell select circuit.
The memory cell array includes a plurality of memory cells arranged in a matrix.
The memory cell array includes a regular memory cell block, and a redundant memory cell block. The redundant memory cell block is provided corresponding to a regular memory cell block to replace a defective memory cell in a corresponding regular memory cell block.
The memory cell select circuit selects either a regular memory cell in a regular memory cell block or a redundant memory cell in a redundant memory cell block according to an address signal.
The memory cell select circuit includes a redundancy determination circuit that determines whether to replace with a redundant memory cell or not by dividing the address signal into a plurality of signal groups and comparing with a defective bit address prestored for each signal group.
According to another aspect of the present invention, a synchronous semiconductor memory device receiving an address signal of a plurality of bits in synchronization with an external signal includes a clock circuit, a memory cell array, and a memory cell select circuit.
The clock circuit generates an internal clock signal in response to an external clock signal. The memory cell array includes a plurality of memory cells arranged in a matrix.
The memory cell array includes a regular memory cell block and a redundant memory cell block. The redundant memory cell block is provided corresponding to a regular memory cell block to replace a defective memory cell in
Nakamura Hiroya
Ooishi Tsukasa
Leydig , Voit & Mayer, Ltd.
Mitsubishi Denki & Kabushiki Kaisha
Tu Christine T.
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