Synchronous self refresh exit control method and circuit in...

Details Synchronous self refresh exit control method and circuit in... Synchronous self refresh exit control method and circuit in...

2005-11-01

2005-11-01

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233100

Reexamination Certificate

active

06961278

ABSTRACT:
A self refresh control device, for use in a semiconductor memory device, comprises a self refresh entry unit having at least one clock buffer for generating a self refresh entry signal in response to an external control signal, wherein the clock buffer generates a clock signal in response to an external clock signal and a clock buffer enable signal; a self refresh exit unit for generating a first self refresh exit signal in response to the external control signal and generating a second self refresh exit signal synchronized with the clock signal; a clock buffer controller for generating the clock buffer enable signal in response to the first self refresh exit signal; and a self refresh signal generator for generating a self refresh signal in response to the self refresh entry signal and the second self refresh exit signal.

REFERENCES:
patent: 6081468 (2000-06-01), Taira et al.
patent: 6421281 (2002-07-01), Suzuki
patent: 2000-030438 (2000-01-01), None
patent: 10-2001-0026122 (2001-04-01), None

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