Synchronous read only memory device

Details Synchronous read only memory device Synchronous read only memory device

1998-07-29

1999-11-16

Hoang, Huan

Static information storage and retrieval

Read only systems

Semiconductive

365233, 3652385, 365239, G11C 1700

Patent

active

059869186

ABSTRACT:
A read only memory device having a given burst length comprises: a memory cell array having a plurality of memory cells, each of the memory cell storing a data bit; a pass gate circuit having a plurality of pass gate blocks assigned to a plurality of bit lines coupled to the memory cells; a sense amplifier circuit having a plurality of sense amplifiers connected to the pass gate blocks with a given ratio thereof; decoding means for causing the pass gate circuit to transfer a given number of the data bits from the memory cells to the sense amplifier circuit; and means for receiving the data bits from the sense amplifier circuit and for outputting a plurality of data bits corresponding to the burst length in a given operation mode. The memory device preferably conducts in a sequential mode or interleave mode, with a pipelined data output configuration according to the burst length.

REFERENCES:
patent: 5572481 (1996-11-01), Wilson
patent: 5581512 (1996-12-01), Kitamura

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