Synchronous random access memory

Details Synchronous random access memory Synchronous random access memory

2000-01-04

2001-12-04

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Read/write circuit

C365S230080

Reexamination Certificate

active

06327188

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to synchronous random access memories (hereinafter referred to as synchronous RAMs), and more specifically, to a high speed synchronous RAM used for improving the speed performance of a computer.
2. Description of the Background Art
A synchronous RAM is a memory which operates in synchronization with an externally applied signal. A typical example of such a synchronous RAM is a synchronous static random access memory (hereinafter referred to as synchronous SRAM).
Synchronous SRAMs are used for cache memories provided for improving speed performance in computers of various levels such as supercomputer, large size calculator, work station, and personal computer.
Conventional synchronous SRAMs as such are disclosed in Japanese Patent Laying-Open No. 2-137189, Japanese Patent Publication No. 1-58591, and Japanese Patent Laying-Open No. 62-250583.
Japanese Patent Laying-Open No. 2-137189 discloses that a plurality of circuits in a memory are formed into a latch and controlled with a clock, in order to reduce cycle time. Japanese Patent Publication No. 1-58591 discloses that an input latch circuit for address signals and a circuit for latching outputs from a decode circuit are operated in a complementary manner with a single clock signal. Japanese Patent Laying-Open No. 62-250583 discloses producing of an internal write enable signal in response to an externally applied clock signal.
Now, a conventional general synchronous SRAM will be described.
FIG. 9
is a block diagram showing an example of a conventional synchronous SRAM.
Referring to
FIG. 9
, the synchronous SRAM includes a memory core
50
, latch circuits
11
,
12
,
16
~
19
,
25
, and
26
, buffer circuits
63
,
67
, and
68
, inverter circuits
64
and
69
, and a tri-state buffer circuit
68
.
Memory core
50
includes a memory cell array
51
, a decoder
52
, a read circuit
53
and a write circuit
54
. Decoder
52
, read circuit
53
, and write circuit
54
are connected to memory cell array
51
.
An externally applied address signal ADD is input from an address input pin
1
, and applied to decoder
52
as an internal address signal RADD through buffer circuit
61
, and latch circuits
11
and
16
. An externally applied write enable signal NWE input from a control input pin
2
is applied to read circuit
53
and write circuit
54
as an internal write enable signal NWEin through buffer circuit
62
, and latch circuits
12
and
17
.
Read data RD output from read circuit
53
is applied to a data input/output pin
4
through latch circuits
18
,
19
and tri-state buffer circuit
68
and externally output therefrom. Thus, tri-state buffer
68
acts as an output buffer circuit. Externally applied write data is input from input/output pin
4
and is applied to write circuit
54
as write data WD through buffer circuit
67
, and latch circuits
26
and
25
.
An externally applied clock signal K is input from a clock input pin
5
. Buffer circuit
63
outputs an internal clock signal PH
1
in response to external clock signal K. Inverter
64
outputs an internal clock signal PH
2
which is the inverse of internal clock signal PH
1
in response to external clock signal K.
Latch circuits
16
,
17
,
19
and
25
operate in response to internal clock signal PH
1
. Latch circuits
11
,
12
,
18
, and
26
operate in response to internal clock signal PH
2
. These latch circuits each propagate input data to each output if an applied internal clock signal is in H level, and latch data for output if the applied internal clock signal is in L level.
In
FIG. 9
, the latch circuits which receive internal clock signal PH
1
are denoted by “PH
1
”, and the latch circuits which receive internal clock signal PH
2
are denoted at “PH
2
” for ease of illustration.
An external output enable signal NOE input from a control input pin
3
is inverted at inverter
69
and applied to tri-state buffer circuit
68
as a control signal. The three states of tri-state buffer circuit
68
are controlled in response to the control signal. More specifically, tri-state buffer
68
is activated if external enable signal NOE is in L level, and attains a high impedance state if external output enable signal NOE is in H level.
Other conventional synchronous SRAMs will be described.
FIG. 10
is a block diagram showing the structure of another conventional synchronous SRAM.
Referring to
FIG. 10
, unlike the synchronous SRAM shown in
FIG. 9
, the synchronous SRAM is not provided with latch circuit
26
as shown in FIG.
9
. Therefore, the synchronous SRAM shown in
FIG. 10
which operates basically the same as the synchronous SRAM in
FIG. 9
has a slightly different timing spec. for the absence of latch circuit
26
.
The synchronous SRAMs shown in
FIGS. 9 and 10
each do not have any latch circuit which operates in response to internal clock signal PH
1
or PH
2
in the path until input of external output enable signal NOE into tri-state buffer circuit
68
. Tri-state buffer circuit
68
operates asynchronously with respect to external clock signal K.
Besides, a latch circuit may be provided in the path until input of external output enable signal NOE into tri-state buffer
68
. Such a synchronous SRAM has a slightly different timing spec. from the synchronous SRAMs in
FIGS. 9 and 10
.
Operations of the conventional synchronous SRAMs shown in
FIGS. 9 and 10
will be described. As described above, the synchronous SRAMs shown in
FIGS. 9 and 10
operate basically in the same manner, and therefore the synchronous SRAM shown in
FIG. 10
will be described by way of illustration.
FIG. 11
is a timing chart for use in illustration of the synchronous SRAM shown in FIG.
10
. Illustrated in
FIG. 11
are external clock signal K, external write enable signal NWE, external address signal ADD, data input/output signal DQ and external output enable signal NOE.
Herein, the period in which external clock signal K attains H level is called first phase Ph
1
, and the period in which external clock signal K attains L level is called second phase Ph
2
. First phase Ph
1
corresponds to the period in which internal clock signal PH
1
attains H level, and second phase Ph
2
corresponds to the period in which internal clock signal PH
2
attains H level.
First phase Ph
1
and second phase Ph
2
as such constitute one cycle for operation of the synchronous SRAM.
In
FIG. 11
, a first cycle CY
1
to a seventh cycle CY
7
are shown. In the series of cycles, writing, reading, writing, reading and reading operations are sequentially executed. The writing operations herein include not only writing of data into memory cell array
51
but also operations related to input of external address signal ADD and write data for the data writing.
The reading operations herein include not only data reading from memory cell array
51
but also operations related to input of an external address signal for the data reading and external output of the read data.
For the above writing operations, cycles for writing of data into memory cell array
51
are denoted by “WRITE” in the figure, and for the above reading operations, cycles for data reading from memory cell array
51
are denoted by “READ”. Data input/output to/from data input/output pin
4
is illustrated at DQ.
In operation, it is assumed that external address signal ADD passes through latch circuit
11
and external write enable signal NWE passes through latch circuit
12
in the second phase of a cycle immediately before first cycle CY
1
.
Then in the first phase Ph
1
of first cycle CY
1
, internal clock signal PH
2
attains L level. Thus, external address signal ADD and external write enable signal NWE are latched by latch circuits
11
and
12
, respectively.
In first phase Ph
1
, internal clock signal PH
1
attains H level. Thus, the latched external address signal ADD is applied to decoder
52
as internal address signal RADD through latch circuit
16
. At the time, the latched external write enable signal NWE is applied as interna

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