Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
1999-08-31
2002-09-10
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S400000, C713S401000, C713S500000, C327S146000, C327S150000, C327S156000, C327S159000
Reexamination Certificate
active
06449728
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to computer systems and, more specifically, to computer system clock synchronization.
BACKGROUND OF THE INVENTION
A conventional computer system includes a clock that controls the timing of the computer functions it performs. Such a computer system may have two clocks controlling the functions performed by two separate clock domains. For example, a computer system may have a primary clock controlling a clock domain devoted to processor functions and a secondary clock controlling a clock domain devoted to input/output functions. In such an environment, the primary clock and secondary clock must be synchronized to function correctly.
Such a computer system typically is implemented on a circuit board. The circuit board may contain a subsystem implemented with a chip such as an ASIC (Application Specific Integrated Circuit) that has its own internal clock control. In such a system, the ASIC may also have two internal primary and secondary clocks. In such a system, the external system clocks must be synchronized with the internal ASIC clocks. Also, the internal primary and secondary clocks must be synchronized to function correctly. Thus, a means is desirable for providing an efficient and effective synchronization of all four clock domains.
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patent: 5295164 (1994-03-01), Yamamura
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Gaffin Jeffrey
Park Ilwoo
Pickens S. Kevin
Wills Kevin D.
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