Synchronous pseudo static random access memory

Details Synchronous pseudo static random access memory Synchronous pseudo static random access memory

2007-11-27

2007-11-27

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S203000

Reexamination Certificate

active

11326177

ABSTRACT:
A latency control circuit for use in a semiconductor memory device includes a precharge unit for outputting a precharge reset signal based on a refresh signal and a normal active signal, wherein the precharge reset signal is used for extending a latency during a burst read period which includes a refresh cycle; a refresh cycle detector for detecting the refresh cycle in response to a latency setting signal and the precharge reset signal to thereby output a latency extension signal; a latency decoder for decoding an external address to thereby output a plurality of preliminary latency signals; and a latency controller for outputting a plurality of latency signals in response to the preliminary latency signal and the latency extension signal.

REFERENCES:
patent: 5835956 (1998-11-01), Park et al.
patent: 5903916 (1999-05-01), Pawlaowski et al.
patent: 6711083 (2004-03-01), Demone
patent: 6853602 (2005-02-01), Huang
patent: 6891772 (2005-05-01), Demone
patent: 7042777 (2006-05-01), Oh
patent: 2002-230973 (2002-08-01), None
patent: 2004-318500 (2004-11-01), None

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