Synchronous memory tester

Static information storage and retrieval – Read/write circuit – Testing

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Details

365222, 365233, G11C 700

Patent

active

059149027

ABSTRACT:
An automated, portable, and time conservative memory test system for identifying test parameters including type, control line configuration, depth, width, access time, and burst features of any one of a wide variety of synchronous memories including SDRAMs and SGRAMs, and whether an IC chip, bank, board or module, without requiring hardware modifications or additions to the memory device being identified, and without requiring storage of test patterns or characterizing data in the memory device.

REFERENCES:
patent: 5402389 (1995-03-01), Flannagan et al.
patent: 5539692 (1996-07-01), Kajigaya et al.
patent: 5587950 (1996-12-01), Sawada et al.

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