Synchronous memory system with asynchronous internal memory oper

Details Synchronous memory system with asynchronous internal memory oper Synchronous memory system with asynchronous internal memory oper

1995-05-31

1998-01-06

Teska, Kevin J.

395551, G06F 1200

Patent

active

057064741

ABSTRACT:
A memory system is provided which is capable of eliminating deterioration in a processing rate due to possible signal delays between an input/output circuit and memory blocks. Complication of design is also reduced, especially when the scale and chip area of the memory system increase. A memory chip includes a plurality of memory array blocks each including an address buffer and an address counter, and operates on the basis of a local clock cycle. A control circuit is synchronous with a clock of an external device, and synchronous data-transfer circuitry includes a buffer which modulates the transfer rate of serial data which arrives from a memory array block at a local clock cycle so as to be synchronous with the clock of the control circuit. External clock signal lines are not distributed to the memory array blocks.

REFERENCES:
patent: 4513374 (1985-04-01), Hooks, Jr.
patent: 5404338 (1995-04-01), Murai et al.
patent: 5498990 (1996-03-01), Leung et al.
patent: 5550783 (1996-08-01), Stephens, Jr. et al.

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