Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1998-06-09
2002-12-24
Portka, Gary J (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S150000, C711S158000, C710S244000
Reexamination Certificate
active
06499087
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the shared usage of synchronous memory by a plurality of agents, i.e., processors.
2. Background of Related Art
With the ever-increasing speeds of today's processors, memory designs have attempted to meet the required speed requirements. For instance, synchronous memory such as static random access memory (SRAM) and dynamic random access memory (DRAM) are commonly available synchronous types of memory.
Synchronous memory technology is currently used in a wide variety of applications to close the gap between the needs of high-speed processors and the access time of a synchronous memory such as dynamic random access memory (DRAM). Synchronous memory, e.g., SDRAM technology, combines industry advances in fast dynamic random access memory (DRAM) with a high-speed interface.
Functionally, an SDRAM resembles a conventional DRAM, i.e., it is dynamic and must be refreshed. However, the SDRAM architecture has improvements over standard DRAMs. For instance, an SDRAM uses internal pipelining to improve throughput and on-chip interleaving between separate memory banks to eliminate gaps in output data.
The idea of using a SDRAM synchronously (as opposed to using a DRAM asynchronously) emerged in light of increasing data transfer demands of high-end processors. SDRAM circuit designs are based on state machine operation instead of being level/pulse width driven as in conventional asynchronous memory devices. In addition, synchronous memory access techniques improve the margin to system noise because inputs are not level driven. Instead, the inputs are latched by the system clock. Since all timing is based on the same synchronous clock, designers can achieve better specification margins. Moreover, since the SDRAM access is programmable, designers can improve bus utilization because the processor can be synchronized to the SDRAM output.
The core of an SDRAM device is a standard DRAM with the important addition of synchronous control logic. By synchronizing all address, data and control signals with a single clock signal, SDRAM technology enhances performance, simplifies design and provides faster data transfer.
Similar advantages hold for other types of synchronous memory, e.g., synchronous SRAM (SSRAM) or even synchronous read only memory (ROM).
Synchronous memory requires a clock signal from the accessing agent to allow fully synchronous operation with respect to the accessing agent. If more than one agent is given access to a shared synchronous memory, each agent must conventionally supply its own clock signal to the synchronous memory. Unfortunately, the clock signals from separate agents are not conventionally synchronous or in phase with one another. Therefore, as the synchronous memory shifts from the use of one clock signal to another, delays or wait states must be added before the new agent's clock signal can be used to access the synchronous memory. Moreover, arbitration schemes between a plurality of agents for conventional memory systems evidences that the performance of one agent may suffer more than another agent sharing the same memory, particularly if the memory accesses are disproportionately distributed among the accessing agents.
Some synchronous memory devices have the capability to provide burst input/output (I/O), particularly for the optimization of cache memory fills at the system frequency. Advanced features such as programmable burst mode and burst length improve memory system performance and flexibility in conventional synchronous memories, and eliminate the need to insert wait states, e.g., dormant clock cycles, between individual accesses in the burst.
Conventional SRAM devices include independent, fixed memory sections that can be accessed individually or in an interleaved fashion. For instance, two independent banks in an SRAM device allow that device to have two different rows active at the same time. This means that data can be read from or written to one bank while the other bank is being precharged. The setup normally associated with precharging and activating a row can be hidden by interleaving the bank accesses.
FIG. 6
shows a conventional un-shared synchronous memory system having a single agent A and a synchronous memory, e.g., SRAM
502
. The single agent A communicates with the synchronous memory using appropriate address, data and control buses (ADC)
506
, and one or more clock signals
504
. Because the synchronous memory
502
has only the single accessing agent A, the synchronous memory
302
needs only to contend with access from a single source.
Unfortunately, systems utilizing a plurality of agents conventionally include separate memory systems for each agent, causing wasted memory resources in the event that one or more agents are not fully utilizing their available memory.
There is thus a need for synchronous memory systems which allow efficient use of synchronous memory resources by a plurality of agents.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, a shared synchronous memory system comprises a super agent, at least one non-super agent, and a shared synchronous memory. An arbiter-and-switch allows the super agent unarbitrated access to the shared synchronous memory and allows the non-super agent an open window of access to the shared synchronous memory when the super agent is not accessing the shared synchronous memory.
A method of sharing synchronous memory among a plurality of agents in accordance with another aspect of the present invention comprises the assignment of one of a plurality of agents with super agent status and the others of the plurality of agents with non-super agent status. The super agent is allowed to access a shared synchronous memory without arbitration, and the non-super agents arbitrate for access to the shared synchronous memory.
REFERENCES:
patent: 3967246 (1976-06-01), House
patent: 5021950 (1991-06-01), Nishikawa
patent: 5134613 (1992-07-01), Virzi et al.
patent: 5179667 (1993-01-01), Iyer
patent: 5752010 (1998-05-01), Herbert
patent: 5784582 (1998-07-01), Hughes
patent: 5845139 (1998-12-01), Fischer et al.
patent: 5867180 (1999-02-01), Katayama et al.
patent: 5872936 (1999-02-01), Eckstein
patent: 5920894 (1999-07-01), Plog et al.
patent: 5987574 (1999-11-01), Paluch
patent: 5996051 (1999-11-01), Mergard
patent: 6163831 (2000-12-01), Kermani
patent: 6263425 (2001-07-01), Falik
Fadavi-Ardekani Jalil
Kermani Bahram
Niescier Richard J.
Soto Walter G.
You Fan
Agere Systems Guardian Corp.
Bollman William H.
Portka Gary J
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