Synchronous memory interface

Details Synchronous memory interface Synchronous memory interface

1997-11-06

1999-06-29

Nelms, David

Static information storage and retrieval

Read/write circuit

Signals

365233, 3652335, G11C 700

Patent

active

059177616

ABSTRACT:
A synchronous memory interface feeds back a buffered (34) clock signal to a microcontroller (20) to simplify and improve output hold time for the memory (38). An output delay circuit (36) in the microcontroller (20) is controlled by the same delayed clock signal as the synchronous memory (38). This delay circuit (36) selectively delays memory signals to the synchronous memory (38) from the microcontroller delay circuit (36). The use of flip-flops (40, 44) in the delay circuit (36) provides a mechanism for scan testing. This enables three different selectable modes of operation of the delay circuit (36) providing flexibility in interfacing in different environments.

REFERENCES:
patent: 5646904 (1997-07-01), Ohno et al.
patent: 5652733 (1997-07-01), Chen et al.
patent: 5768177 (1998-06-01), Sakuragi
patent: 5781499 (1998-07-01), Koshikawa
patent: 5781500 (1998-07-01), Oh

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