Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-04-12
2001-02-06
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S203000, C365S230060
Reexamination Certificate
active
06185151
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to synchronous memory devices, and more particularly, to a synchronous memory device in which data are written to memory cells in response to activation of a write command, and a data write method using the same.
2. Description of the Related Art
At present, for the purpose of improving the access time of memory devices, synchronous memory devices in which operation is synchronized with an external system clock have been developed. In synchronous memory devices, a data write or read operation is controlled based on the external system clock signal. Thus, if the frequency of the system clock signal increases due to an increase in the operating speed of an external system that outputs the clock signal, the operating speed for the data write or read must be increased in response to the frequency increase.
In a general synchronous memory device, a reduced access time to the memory device relative to the system clock frequency during a data read operation can be implemented by increasing column address strobe (CAS) latency. CAS latency is defined as the period of time from the activation of a CAS signal to the output of data. That is, as the operating frequency of an external system increases due to a high operating speed thereof, the data can be output in synchronism with the system clock by increasing the CAS latency.
During the data read operation, although the read operating speed of the synchronous memory device can not increased, data can be output in synchronization with the system clock having an increased frequency, as long as the point in time at which data is read from the point in time at which the CAS signal was generated, that is, the CAS latency, is increased. This is possible because during the data read operation, the address of the succeeding memory cell to be read can be input in advance while the present data is being processed.
However, unlike the data read operation, during the data write operation, the process of writing the present data must be completed before inputting the succeeding data process. However, the data write period of time, i.e., from the activation of a write command to the data writing to the memory cell, is shorter than the system clock cycle, so that one write operation can be completed within the system clock cycle.
However, as the system clock cycle is shortened with the increased operating speed of the system, the data write operation cannot be completed within the system clock cycle. Thus, the maximum operating speed of the system is restricted by the write cycle of the memory device therein.
SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a synchronous memory device capable of performing a write operation in synchronism with a reference clock signal. The synchronous memory device comprises: a memory cell array including a plurality of memory cells arranged in rows and columns; a precharge circuit for precharging a data input/output line which transmits data to be written to the memory cells, with a predetermined voltage level; a column selection circuit for writing the data transmitted to the data input/output line to a selected memory cell, in response to activation of a column selection signal; and a mode register set for setting write cycle modes. The activation cycle of the column selection signal is determined according to the write cycle modes programmed in the mode register set.
Preferably, one of the write cycle modes is selected by a user. The write cycle modes may be classified according to the number of reference clock cycles for a period of time from the input of a write command to the writing of data to the memory cell.
In another embodiment, the present invention provides a synchronous memory device for initiating a write operation of data to a memory cell in response to the activation of a column selection signal after a write command is input, and terminating the write operation in response to inactivation of the column selection signal. The synchronous memory device comprises: a control signal generating circuit for receiving a system clock signal, a column address strobe signal and a write enable signal to generate a column selection line disable signal which disables the column selection signal; and a mode register set into which write cycle modes are programmed, one of the write cycle modes being selected in response to an address designated by a user. The activation cycle of the column selection signal is determined according to the write cycle modes which are programmed into the mode register based on the reference clock cycle.
Preferably, the control signal generating circuit comprises: a clock buffer for generating a reference clock signal based on which data are input and output, in response to the system clock signal; a column address strobe buffer for generating a column selection control signal that is enabled for a predetermined period of time in response to activation of the column address strobe signal; and a write enable buffer for generating a write master signal that is enabled for a predetermined period of time in response to the activation of the write enable signal, and generating a write master delay signal, which is delayed by a predetermined period of time relative to the write master signal, in the second write cycle mode. Also, the control signal generating circuit further comprises: a precharge signal generating circuit for precharging a data input/output line in response to the reference clock signal, and generating a precharge signal which is disabled for a predetermined period of time during which the write master delay signal is enabled; and a column selection line disable signal generating circuit for generating a column selection line disable signal that disables a column selection line, in response to the precharge signal and the column selection control signal.
According to another aspect of the present invention, there is provided a data write method for a synchronous memory device for writing data to a particular memory cell in response to activation of a column selection signal. The number of reference clock cycles required for execution of a write command is programmed and then stored in at least one bit of a mode register set of the synchronous memory device. Upon receiving a write enable signal, which changes a mode to a write mode, a write master signal and a write master delay signal are generated. An input/output line precharge signal is generated in response to the reference clock signal and the write master delay signal, wherein the precharge signal is disabled for the execution of the write command if the programmed number of reference clock cycles is more than one. A column selection line disable signal, which is disabled in response to activation of the precharge signal, is generated, and a column selection signal, which is enabled in response to the activation of the column selection line corresponding to a decoded address, and is disabled in response to the column selection line disable signal, is then generated.
Thus, the system clock frequency information is classified into write cycle modes and programmed in a mode register set, so that the number of cycles for write operation can be varied. Accordingly, the operating speed of the system can be increased to a maximum level which is not limited by the write cycle time of the memory device.
REFERENCES:
patent: 4394753 (1983-07-01), Penzel
patent: 5844859 (1998-12-01), Iwamoto et al.
Heid David W.
Hoang Huan
Samsung Electronics Co,. Ltd.
Skjerven Morrill & MacPherson LLP
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