Synchronous memory device with prefetch address counter

Details Synchronous memory device with prefetch address counter Synchronous memory device with prefetch address counter

2000-06-14

2004-03-16

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S219000, C365S230040, C365S239000

Reexamination Certificate

active

06708264

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-168615, filed Jun. 15, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a synchronous memory device using the techniques for accessing data items simultaneously in one cycle, or so-called prefetching techniques, and more particularly to the configuration of an address counter.
The recent trend of semiconductor memory technology has been toward using a DRAM with a special function for burst data transfer, such as a DRAM conforming to Rambus specifications or a synchronous DRAM (hereinafter, referred to as an SDRAM), in place of a conventional general-purpose DRAM in order to bridge the gap between the controller side including the CPU and MPU and the memory side. As for SDRAMs, Double Data Rate (DDR) specifications have been established and products conforming to the DDR specifications are going to be placed on the market. In the DDR specifications, not only the frequency of the basic clock (CLK) is raised, but also the input and output of data are synchronized with both of the leading edge and trailing edge of the basic clock as in a Rambus DRAM. In contrast, conventional Single Data Rate (SDR) specifications are such that the input and output of data are synchronized with the leading edge of the basic clock.
Now, consider the column accessing operation in a SDRAM. If the frequency of the basic clock is 100 megahertz, its period is 10 nanoseconds. In the case of SDR, the counting up of the address, column selection, and data transfer have to be performed in the 10-nanosecond period. Furthermore, when an attempt is made to increase the frequency of the basic clock or to carry out a DDR operation, a series of column access operations must be performed in the shortest time ranging from 3.5 to 4 nanoseconds. Even if a pipeline operation were performed or the manufacturing process of semiconductor devices were improved, the column accessing operation in such a short time would a very severe condition very difficult to satisfy using the present technology. Considering the fact that the CAS cycle time (tPC) of a conventional DRAM is about 12 to 15 nanoseconds, it is extremely difficult to realize such a short column accessing operation.
To solve this problem, a technique called prefetching has been introduced recently.
Semiconductor memory devices using the prefetching techniques have been disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 10-340579 and Jpn. Pat. Appln. KOKAI Publication No. 11-66878.
In the SDRAM, for example, when a column access operation is performed for reading, all the addresses to be accessed can be determined beforehand from the preset addressing mode and burst length at the time when the start address (hereinafter, referred to as the Tap address) supplied simultaneously with a read command is taken in. When the first Tap address is accessed, the subsequent addresses are accessed simultaneously, thereby reading part of the data, which gives a time margin to the column accessing operation of the second data item and later. Because a margin is given as CAS latency according to the SDRAM specifications to the time from when the read command is received until the data in the first Tap address is read, combining with a pipeline operation enables the data to be outputted continuously in a short cycle time. When too many bits have been prefetched, this makes timing control of the internal data lines complex. In addition, for example, a burst length smaller than the number of data items prefetched has been specified, the read-out data might be discarded uselessly. To avoid this, it is common practice to minimize the number of bits to be prefetched. From the viewpoint of the frequency of the present basic clock, two-bit prefetching has been considered to be able to cope with the cycle time sufficiently.
FIG. 1
is a block diagram of the address counter in a conventional semiconductor memory device without prefetching, which helps to explain the synchronous memory device. When the direction of depth of the column address is n+1 bits, the number of counters is n+1 from A<
0
> to A<n> (hereinafter, <n> represents an accompanying character for bit order and <m:n> indicates the consecutive bit orders from bit m to bit n, where m and n are integers). Signals ALTC<n:
0
>, CTCLK, TAPLTC, and INTLV are inputted to each of the counters
11
-
1
to
11
-n. ALTC<n:
0
> is a Tap address latched inside and is inputted to the counters
11
-
0
to
11
-n corresponding to the accompanying characters. CTCLK is a clock signal for incrementing the counter and TAPLTC is a signal for transferring the Tap address. INTLV is a signal indicating an addressing mode. When the signal is at the high level, this means an interleave mode. When it is at the low level, this means a sequential mode. The counters
11
-
0
to
11
-n for the respective bits output a counter address CA<n:
0
> and at the same times a carry signal CRY<n−1:
0
> in such a manner that the counter address and carry signal are inputted to the counter at the next stage. At this time, the carry input to the counter
11
-
0
is fixed to a power supply (VDD) so that the counter may count up in each cycle. On the other hand, the carry of the counter
11
-n is not outputted because there is no following stage.
FIG. 2
is a conceptual diagram showing the configuration of an address counter, which helps explain a conventional synchronous memory device that effects two-bit prefetching. To effect two-bit prefetching, two consecutive addresses are generally accessed and therefore two sets of counters
12
A and
12
B are needed. At the address input sections of the two sets of counters
12
A and
12
B, +1 adders
13
A and
13
B are provided, respectively. The output of an adder control circuit
14
determines which of the adders
13
A and
13
B is to be enabled.
Now, consider the operation of the adders
13
A and
13
B by reference to
FIGS. 3A
to
3
D. In an SDRAM, two modes, the interleave mode and sequential mode, are defined as the addressing mode.
FIGS. 3A and 3B
show the interleave mode and
FIGS. 3C and 3D
show the sequential mode. In each mode, a total of four addressing patterns can be considered, depending on whether the Tap address is even (here, “0000”) or odd (here, “001”). In
FIGS. 3A
to
3
D, three-bit addressing is shown for the sake of simplification. In each counter cycle, an even address whose least significant bit is “0” is written separately from an odd address whose least significant bit is “1.”
Two addresses written in one line (the part enclosed by a broken line) are assumed to be two-bit prefetched. In this case, the two sets of address counters
12
A and
12
B generate an even address and an odd address in each cycle, respectively. Of each counter set, the one-bit output corresponding to the low order is fixed to “0” or “1” and therefore is not needed. To effect three-bit addressing, the counter has only to contain two bits.
In the operation of the adders
13
A and
13
B in the interleave mode, when the Tap address is even (A<
0
>=“0”), the address for the data to be read first is generated at the even counter and the address for the second data to be accessed simultaneously in two-bit prefetching is generated at the odd counter. At this time, because the counter address of the even counter is allowed to have the same value (000) as that of the Tap address, the adder on the even-number side need not operate and the Tap address has only to be transferred directly to the counter. The start address of the odd counter is such that the least significant bit is inverted in the Tap address (001). Since the least significant bit in the address has been fixed to “1” beforehand, the adder need not be operated and the remaining bits in the Tap address excluding the least significant bit have onl

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