Synchronous memory device utilizing request protocol and method

Details Synchronous memory device utilizing request protocol and method Synchronous memory device utilizing request protocol and method

1999-03-05

2000-10-03

Shin, Christopher B.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

36518902, 36523102, 365233, 710 3, 710 9, 710 36, 710 51, 710 61, 710129, G06F 1300

Patent

active

061286966

ABSTRACT:
A method of operation of a synchronous memory device having at least one memory section which includes a plurality of memory locations. The method comprises receiving an external clock signal having a fixed frequency, receiving a read request, including addressing information, synchronously with respect to the external clock signal, initiating an internal memory addressing operation, in response to the read request, and outputting data onto the external bus synchronously with respect to the external clock signal. The synchronous memory device may include interface circuitry, coupled to an external bus, to receive a write request packet synchronously with respect to an external clock. The write request packet may include N bits of information and the external bus includes M number of signal lines wherein N is substantially greater than M. The synchronous memory device may also include input receiver circuitry, coupled to the external bus, to receive data from the external bus synchronously with respect to the external clock wherein the received data is stored in the synchronous memory device in response to the write request packet.

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