Synchronous memory device having advanced data align circuit

Details Synchronous memory device having advanced data align circuit Synchronous memory device having advanced data align circuit

2007-10-23

2007-10-23

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

Reexamination Certificate

active

10750602

ABSTRACT:
A semiconductor device for performing an N-bit prefetch operation, N being a positive integer includes a data strobe buffering means for generating N number of align control signals based on a data strobe signal and a external clock signal; a receiving block in response to N−1 number of the align control signals for receiving N-bit data and outputting the N-bit data in a parallel fashion; and a outputting block in response to the remaining align control signal for receiving the N-bit data in the parallel fashion and synchronizing the N-bit data with the remaining align control signal having a N/2 external clock period to thereby generating the synchronized N-bit data as a prefetched data.

REFERENCES:
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patent: 6260097 (2001-07-01), Farmwald et al.
patent: 2001/0004335 (2001-06-01), Murakami

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