Synchronous memory device

Details Synchronous memory device Synchronous memory device

2006-08-29

2009-06-30

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Addressing

Using selective matrix

C365S189050, C365S194000

Reexamination Certificate

active

07554878

ABSTRACT:
A synchronous memory device, which includes a read command buffer, a replica circuit, and a latency circuit. The read command buffer provides a read signal in response to a read command. The replica circuit provides a transfer signal whose time difference with respect to the feedback clock signal is substantially identical to a period that it takes a read command buffer to provide the read signal. The latency circuit receives the read signal, and provides a latency signal having a difference of a predetermined time corresponding to CAS latency with respect to the read signal in response to the transfer signal.

REFERENCES:
patent: 2004/0081013 (2004-04-01), Lee et al.
patent: 2006/0077751 (2006-04-01), Oh et al.
patent: 2000-293259 (2000-10-01), None
patent: 2003-044349 (2003-02-01), None
patent: 1020040095956 (2004-11-01), None

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