Synchronous interface to a self-timed memory array

Details Synchronous interface to a self-timed memory array Synchronous interface to a self-timed memory array

1997-12-31

2000-05-09

Lane, Jack A

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

711 3, G06F 1200, G11C 800

Patent

active

060612932

ABSTRACT:
A synchronous interface to a self-timed memory array includes one or more address bus inputs and a first latch stage that includes one or more latches. Each of the latches of the first latch stage includes an input coupled to one of the address bus inputs and a first output. The synchronous interface further includes a second latch stage that includes a plurality of latches. Each of the latches of the second latch stage includes an input coupled to one of the first outputs of the first latch stage and a second output coupled to the memory array.

REFERENCES:
patent: 5511033 (1996-04-01), Jung
patent: 5701436 (1997-12-01), Nagashima et al.
patent: 5802596 (1998-11-01), Shinozaki

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