Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
1996-06-24
2001-02-06
Follansbee, John A. (Department: 2783)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C709S248000, C710S061000
Reexamination Certificate
active
06185693
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
The present United States patent application is related to the following United States patent applications incorporated herein by reference:
Application Ser. No. 08/262,087, filed Jun. 17, 1994, entitled “Digital Phase Locked Loop with Improved Edge Detector,” and assigned to the assignee of this application, now U.S. Pat. No. 5,487,095.
Application Ser. No. 08/261,514, filed Jun. 17, 1994, entitled “Self-Timed Interface,” and assigned to the assignee of this application, now U.S. Pat. No. 5,592,553.
Application Ser. No. 08/261,522, filed Jun. 17, 1994, entitled “Multiple Processor Link,” and assigned to the assignee of this application, now U.S. Pat. No. 5,598,442.
Application Ser. No. 08/261,561, filed Jun. 17, 1994, entitled “Enhanced Input-Output Element,” and assigned to the assignee of this application, now U.S. Pat. No. 5,513,377.
Application Ser. No. 08/261,523, filed Jun. 17, 1994, entitled “Attached Storage Media Link,” and assigned to the assignee of this application.
Application Ser. No. 08/261,641, filed Jun. 17, 1994, entitled “Shared Channel Subsystem,” and assigned to the assignee of this application, now U.S. Pat. No. 5,522,088.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an improved method and apparatus for transmitting digital data at high speeds via a parallel data bus, and more particularly, to a method and apparatus to provide a cost effective, scalable communications network for parallel processing systems while eliminating precise bus length and system clock rates as a critical or limiting factor in system design.
2. Description of the Prior Art
As will be appreciated by those skilled in the art, such factors as noise and loading limit the useful length of parallel busses operating at high data rates. In the prior art, the length of the bus must be taken into account in the system design and the bus length must be precisely as specified. Manufacturing tolerances associated with physical communication link (chips, cables, cord wiring, connectors, etc.) and temperature and variations in power supply voltage also limit the data rates on prior art busses comprised of parallel conductors. Further, many prior art computer systems transfer data synchronously with respect to a processor clock, so that a change in processor clock rate may require a redesign of the data transfer bus.
An increasingly popular means of providing low cost, high capacity compute capability is to couple a number of computer resources together via a high speed switch network. This allows them to communicate readily with each other to share work as well as to readily access system resources such as DASD, print servers, file servers, archival systems, boot servers, etc., either directly or via gate-way nodes. Typically the number of such network connections scales at least linearly with the number of nodes and in many cases goes up geometrically. As a result, the link technology is a significant component of the total system in terms of cost, reliability, space, power, and can limit the communication subsystems' performance and hence the total machine's performance.
SUMMARY OF THE INVENTION
An object of this invention is the provision of a cost effective bus data transfer system that can operate at high data transfer rates without tight control of the bus length, and without system clock constraints; a system in which the maximum bus length is limited only by the attenuation loss in the bus.
Another object of the invention is the provision of a general purpose, low cost, high performance, point to point data communication link where the width and speed of the interface can easily be modified to tailor it to specific bandwidth requirements and to specific implementation technologies, including VLSI technologies.
A further object of the invention is the provision of a bus data transfer system that operates a clock speed equal to the data rate.
A more specific object of the invention is the provision of a system that adjusts the phase or arrival time of the incoming data on the receive side so it can be optimally sampled by the local receive clock, compensating for many of the manufacturing tolerances associated with the physical link (chip, cable, card wiring, connectors, etc.) as well as temperature changes and power supply output variations.
A further object of the invention is the provision of a low cost, modular, high bandwidth, highly reliable interconnect for structuring moderately parallel systems comprised of microprocessors as well as for parallel processing machines from just a few processing nodes to thousands of processing nodes.
Still another object of the invention is the provision of a semi-synchronous network linking together a number of processors.
Briefly, this invention contemplates the provision of a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell. At the data rates contemplated in the application of this invention, the propagation delay is significant. However, within limits, the bus length is not critical and is independent of the transmit and received system clock. The phase adjustment can compensate for a skew of up to several bit cells across the width of the bus. The self-timed interface is used to link together a number of processors in a network that is readily scalable.
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Capowski Robert Stanley
Casper Daniel Francis
Desnoyers Christine Marie
Ferraiolo Frank David
Garmire Derrick LeRoy
Augspurger Lynn L.
Follansbee John A.
International Business Machines - Corporation
Venable
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