Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-07-17
2001-08-14
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189011, C365S230030
Reexamination Certificate
active
06275445
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a synchronous integrated memory.
Synchronous memories are distinguished by the fact that data to be written are fed synchronously with an external clock signal and data to be read are output synchronously with the external clock signal. The processing within the memory often takes place with an internal clock signal that differs from the external clock signal. Data to be transferred are usually resynchronized from the external clock signal to the internal clock signal, or vice versa, directly at data connections of the memory, via which data connections the data are received from outside the memory or are output to outside the memory. For this purpose, corresponding synchronizing units are disposed directly adjacent to the data connections. In the event of a write access to the memory, data which are to be written and arrive externally at the data connections synchronously with the external clock signal are resynchronized with the internal clock signal by the synchronizing units before they are fed on corresponding data buses to a cell array within the memory, in order to be stored in memory cells.
The external connections of the memory and thus also its data connections are usually disposed in edge regions of the memory. In the event of a write access, a data bit to be written is transferred from each data connection to the corresponding cell array, in order to be stored there. Since the distances between the individual data connections and the cell array are generally different, the data signals that are communicated in the event of the write access experience propagation delay differences between the various data connections, where the signals are synchronized with the internal clock signal, and the cell array. These propagation delay differences become increasingly apparent at high clock frequencies, which are sought in particular for future memories.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a syrnchronous integrated memory that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the aforementioned propagation delay differences between the data bits to be written which are transferred to the memory cell array are advantageously avoided.
With the foregoing and other objects in view there is provided, in accordance with the invention, a synchronous integrated memory containing a group of memory cells disposed adjacent to one another. At least two data connections for feeding in data signals that are synchronized with an external clock signal are provided. A clock generator is provided having a clock output and generating an internal clock signal available at the clock output. Data lines are connected to the data connections. A synchronizing unit is disposed adjacent to the group of memory cells. The synchronizing unit is connected to the group of memory cells and to the data lines and through which the group of memory cells is connected to the data connections. The synchronizing unit has a clock input connected to the clock output of the clock generator, and, in an event of a write access, synchronizes the data signals that have been fed through the data connections and the data lines with the internal clock signal and feeds the data signals to the group of memory cells.
According to the invention, the synchronizing unit which is provided for resynchronizing the internal clock signal to the data signals fed with the external clock signal to the data connections of the memory is disposed directly adjacent to the memory cell group to which the data communicated with the data signals are intended to be written. Therefore, the data signals received from two data connections which, under certain circumstances, are spatially far apart are transferred maintaining synchronism with the external clock signal from the data connections via the data lines to the cell group. Resynchronization of the data signals from the external clock signal to the internal clock signals by the synchronizing unit does not take place until directly at the cell group. This has the advantage that both data signals which are fed to the memory via different data connections are communicated synchronously with the internal clock signal and without propagation delay differences to the cell group and thus to the memory cells situated therein. The invention can be applied to all writeable synchronous integrated memories, for example to synchronous dynamic random access memories (DRAMs).
The invention has the further advantage that the internal clock signal generated by the clock generator is fed only to the clock input of the synchronizing unit disposed adjacent to the cell group. Whereas, in conventional synchronous memories in which the resynchronization to the internal clock signal is effected at the respective data connection, corresponding synchronizing units are present at each data connection and the internal clock signal has to be fed to each of the units. The corresponding clock generator for the internal clock signal is usually disposed in the center of the integrated memory. In the conventional, decentralized configuration of the synchronizing units at each data connection, the internal clock signal generated by the clock generator has to be fed to each of the synchronizing units. This necessitates long clock lines for the feeding of the internal clock signal, which clock lines are additionally highly ramified as well, particularly if there are a large number of data connections via which data signals are transferred simultaneously to the memory. However, long and highly ramified clock lines lead to a disadvantageous loading on the clock output of the clock generator. This severe loading on the clock generator is avoided by the invention since the synchronizing unit according to the invention is disposed at the cell group and not at the edge of the memory, as is usually the case with the data connections. Moreover, in the case of the invention, only one synchronizing unit is necessary per memory cell group, whereas one synchronizing unit is necessary per data connection in the case of conventional synchronous memories. Since many memories have a large number of data connections, the internal clock signal has to be fed to a large number of data connections in the case of conventional memories, which results in corresponding ramification of the clock lines. By contrast, the memory cells of the memory according to the invention can be combined to form the cell groups such that only a smaller number of synchronizing units is necessary. The groups of memory cells may, for example, be memory cell blocks or multiples of memory cell blocks.
In conventional memories the internal clock signal generated by the clock generator must first be communicated to the synchronizing units disposed at the data connections before the resynchronization of the arriving data signals to the internal clock signal can be effected there. In the case of the invention, by contrast, the synchronizing unit is disposed directly at the cell group and therefore generally has a shorter distance from the clock generator than the data connections. Consequently, the propagation delay of the internal clock signal from the output of the clock generator to the synchronizing unit is shorter than in conventional memories. This enables faster operation of the memory. Furthermore, the data signals to be written are transferred synchronously with the external clock signal from the data connections via the data lines to the synchronizing unit, while the internal clock signal is simultaneously transferred from the clock generator to the synchronizing unit. Therefore, the data to be written have already covered the greatest part of the distance between the data connections and the cell group before the resynchronization to the internal clock signal takes place. This also accelerates the write access in the memory according to the invention.
In accordance with an added feature of the inventio
Dietrich Stefan
Partsch Torsten
Schrogmeier Peter
Weis Christian
Greenberg Laurence A.
Infineon - Technologies AG
Le Vu A.
Lerner Herbert L.
Nguyen Tuan T.
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