Synchronous follow-up apparatus and synchronous follow-up...

Details Synchronous follow-up apparatus and synchronous follow-up... Synchronous follow-up apparatus and synchronous follow-up...

2005-07-29

2008-11-25

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C375S376000

Reexamination Certificate

active

07457979

ABSTRACT:
A synchronous follow-up apparatus includes a PLL portion that outputs a first clock signal, and a control loop portion. The control loop portion includes a reference frequency signal generating portion that outputs a reference frequency signal, a clock signal generating portion that generates a second clock signal having the same frequency as a frequency of the first clock signal based on the reference frequency signal generated by the reference frequency signal generating portion, and a frequency control signal generating portion that generates a frequency control signal to change the frequency of the second clock signal based on a frequency difference between the first clock signal and the second clock signal that occurs after a predetermined time and outputs the frequency control signal to the clock signal generating portion.

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patent: 2002/0180498 (2002-12-01), O'Leary et al.
patent: 2004/0012423 (2004-01-01), Maeda
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patent: 2005/0129158 (2005-06-01), Kuwata
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patent: 03/026133 (2003-03-01), None
“CPRI Specification V2.0, Common Public Radio Interface (CPRI); Interface Specification”, Developed by Ericsson AB, Huawei Technologies Co., Ltd., NEC Corporation, Nortel Networks SA and Siemens AG, Oct. 1, 2004, pp. 1-75.

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