Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2011-08-30
2011-08-30
Elmore, Reba I (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S103000, C711S105000, C711S203000, C711S205000
Reexamination Certificate
active
08010767
ABSTRACT:
A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. The memory can output data from storage registers on the data communication connections during a series of clock cycles to provide a burst of register data. The memory can also provide the register data in accordance to a defined clock latency value. The register data can include status data, operating setting data, manufacture identification, and memory device identification.
REFERENCES:
patent: 5041886 (1991-08-01), Lee
patent: 5537354 (1996-07-01), Mochizuki et al.
patent: 5555526 (1996-09-01), Kim
patent: 5570381 (1996-10-01), Schofield
patent: 5600605 (1997-02-01), Schaefer
patent: 5666321 (1997-09-01), Schaefer
patent: 5696917 (1997-12-01), Mills et al.
patent: 5749086 (1998-05-01), Ryan
patent: 5751039 (1998-05-01), Kauffman et al.
patent: 5764584 (1998-06-01), Fukiage et al.
patent: 5787457 (1998-07-01), Miller et al.
patent: 5825710 (1998-10-01), Jeng et al.
patent: 5892777 (1999-04-01), Nesheiwat et al.
patent: 5903496 (1999-05-01), Kendall et al.
patent: 5917724 (1999-06-01), Brousseau et al.
patent: 5936903 (1999-08-01), Jeng et al.
patent: 5963502 (1999-10-01), Watanabe et al.
patent: 5974514 (1999-10-01), Andrewartha et al.
patent: 5986943 (1999-11-01), Isa
patent: 5995438 (1999-11-01), Jeng et al.
patent: RE36532 (2000-01-01), Kim
patent: 6026465 (2000-02-01), Mills et al.
patent: 6038196 (2000-03-01), Oh
patent: 6064627 (2000-05-01), Sakurai
patent: 6128233 (2000-10-01), Yu et al.
patent: 6137133 (2000-10-01), Kauffman et al.
patent: 6141247 (2000-10-01), Roohparvar et al.
patent: 6151270 (2000-11-01), Jeong
patent: 6480429 (2002-11-01), Jones et al.
patent: 6580659 (2003-06-01), Roohparvar
patent: 6728798 (2004-04-01), Roohparvar
patent: 6785764 (2004-08-01), Roohparvar
patent: 6857042 (2005-02-01), Floman et al.
patent: 7096283 (2006-08-01), Roohparvar
patent: 7603534 (2009-10-01), Roohparvar
patent: 908887 (1999-04-01), None
Keeth, et al., “DRAM circuit design: a tutorial,” IEEE Press, 2001, pp. 16-23, 142-153.
Micron Semiconductor Products, Inc., “2Mb, Smart 5 BIOS-Optimized Boot Block Flash Memory,”Flash Memorywww.micron.com, copyright 2000, Micron Technology, Inc., pp. 1-12.
Micron, “16 Mb: x16 SDRAM”Synchronous DRAM, www.micron.com, copyright 1999 Micron Technology, Inc., pp. 1-51.
Hennessy et al., “Computer Organization and Design: The Hardware/Software Interface”, copyright 1998, Morgan Kaufmann Publishers, Inc., pp. 191-192.
“Computer Dictionary”, copyright 1994, Microsoft Corporation, p. 334.
Elmore Reba I
Lerner David Littenberg Krumholz & Mentlik LLP
Round Rock Research, LLC
LandOfFree
Synchronous flash memory with status burst output does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Synchronous flash memory with status burst output, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous flash memory with status burst output will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2691797