Synchronous dynamic random access memory semiconductor...

Details Synchronous dynamic random access memory semiconductor... Synchronous dynamic random access memory semiconductor...

2000-04-27

2001-05-22

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230030, C365S203000, C365S195000

Reexamination Certificate

active

06236619

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 99-15434, filed on Apr. 29, 1999, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, to a double data rate (DDR) synchronous dynamic random access memory (SDRAM) having a write-interrupt-write function.
DDR SDRAM semiconductor devices each have a write-interrupt-write function. In a DDR SDRAM, data to be written is input from the outside through one group of input/output lines to a memory block. The write-interrupt-write function refers to when the writing of data is interrupted for the writing of data input through another group of input/output lines to the memory block.
In the DDR SDRAM semiconductor device, a period of two clock cycles of an external clock signal is taken to externally input data loaded onto the groups of input/output lines. However, in a conventional DDR SDRAM semiconductor, such a data loading timing is not considered in performing the write-interrupt-write function, with the result that a mis-operation may occur in the DDR SDRAM memory device.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a synchronous dynamic random access memory (SDRAM) semiconductor device capable of accurately performing a write-interrupt-write function.
In one embodiment, the present invention provides a synchronous dynamic random access memory (SDRAM) semiconductor device having a write-interrupt-write function. This SDRAM semiconductor device includes a first memory block for storing data, a first sense amplifier for sensing the data stored in the first memory block, first and second groups of input/output lines, connected to the first sense amplifier, and a write-interrupt-write signal generating portion for receiving an externally input write signal and an internal clock signal, generating a write-interrupt-write signal and providing the write-interrupt-write signal to the first sense amplifier. When externally input data is written to the first memory block through the first group of input/output lines in response to the write signal enabled at a first point in time and the write signal is enabled at a second point in time to write data to the first memory block through the second group of input/output lines, the write-interrupt write signal generator enables the write-interrupt-write signal after a predetermined number of cycles of the internal clock signal from the second point in time at which the write signal is enabled, thereby immediately precharging the first group of input/output lines.
The write-interrupt-write signal generating portion may comprise a signal delay unit for receiving the write signal and the internal clock signal, and for delaying the write signal by a predetermined number of cycles of the internal clock signal in response to the internal clock signal and a pulse signal generator connected to the signal delay unit for generating the write-interrupt-write signal as pulses in response to the internal clock signal and the output from the signal delay unit.
The signal delay unit may further comprise first through fourth transmission gates for receiving the write signal and the internal clock signal, the first through fourth transmission gates being sequentially turned on by the internal clock signal in response to a rising or falling transition of the internal clock signal, and first through fourth latch circuits connected to the first through fourth transmission gates, respectively, for latching the outputs from the first through fourth transmission gates.
The pulse generator may further comprise a first logic circuit for combining the write signal and the internal clock signal, and for outputting the combination of the write signal and internal clock signal, an inverter chain including an odd number of inverters, for receiving the output from the first logic circuit, and a second logic circuit for generating the write-interrupt-write signal by combining the output from the first logic circuit and the output from the inverter chain.
The pulse signal generator preferably generates a write-interrupt-read signal, and the signal delay unit preferably disables the write-interrupt-write signal based on the write-interrupt-read signal. The write-interrupt-write signal is enabled in a write-interrupt-write mode or in a write-interrupt-read mode.
The synchronous dynamic random access memory semiconductor device may further comprise a second memory block for storing data, a second sense amplifier for sensing the data stored in the second memory block, and third and fourth groups of input/output lines, connected to the second sense amplifier. The first and third groups of input/output lines are preferably simultaneously activated or precharged, and the second and fourth groups of input/output lines are preferably simultaneously activated or precharged.
The synchronous dynamic random access memory semiconductor device is preferably a double data rate synchronous dynamic random access memory semiconductor device.
The synchronous dynamic random access memory semiconductor device may further comprise a clock signal converter for converting an external clock into the internal clock.
Therefore, the SDRAM semiconductor device can accurately perform the write-interrupt-write function.


REFERENCES:
patent: 5594704 (1997-01-01), Konishi et al.
patent: 5781496 (1998-07-01), Pinkham et al.

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