Synchronous dynamic random access memory (SDRAM) structure

Details Synchronous dynamic random access memory (SDRAM) structure Synchronous dynamic random access memory (SDRAM) structure

2003-02-13

2004-08-10

Le, Dung A. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000, C257S302000, C257S303000

Reexamination Certificate

active

06774424

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a synchronous dynamic random access memory (SDRAM) structure and a method of fabricating the same. More particularly, the present invention relates to a SDRAM structure having a deep-trench capacitor and a stacked capacitor.
2. Description of Related Art
Memory is a semiconductor storage device for holding programs or data. In general, the number of bits a memory device can store determines the capacity of the device and each memory cell is a basic unit for holding a single bit of data. The memory cells are usually arranged into an array such that each column of memory cells is serially linked together by a single bit line (BL) while each row of memory cells is serially linked together by a single word line (WL). Through a bit line and a word line connection, the location or the address of a particular memory cell is easily pinpointed. In addition, each memory may further include an address decoder for decoding memory addresses and some other peripheral circuits to facilitate memory operation.
In general, the larger the number of memory cells in a memory array, the larger will be the capacity of the memory device. Hence, increasing the number of memory cells per unit surface area of the wafer is a perpetual target for memory device development.
FIG. 1
is a schematic sectional view of a conventional synchronous dynamic random access memory with a stacked capacitor. As shown in
FIG. 1
, a transistor is formed over a substrate
100
. The transistor is a three-terminal device including a gate terminal
102
and a pair of source/drain terminals
106
. The gate
102
is formed over the substrate
100
. A gate insulation layer
104
separates the gate
102
from the substrate
100
. The source/drain terminals
106
are doped regions in the substrate
100
on each side of the gate
102
. One source/drain terminal
106
is electrically connected to a stack capacitor structure
108
. Another source/drain terminal
106
is electrically connected to a bit line
110
. A conventional stack capacitor
108
has a three-layered structure that includes a conductive layer, a dielectric layer and another conductive layer. The entire stack capacitor structure
108
is formed over the substrate
100
.
FIG. 2
is a schematic cross-sectional view of a conventional synchronous dynamic random access memory with a trench capacitor. As shown in
FIG. 2
, a transistor is formed over a substrate
200
. The transistor is a three-terminal device including a gate terminal
202
and a pair of source/drain terminals
206
. The gate
202
is formed over the substrate
200
. A gate insulation layer
204
separates the gate
202
from the substrate
200
. The source/drain terminals
206
are doped regions in the substrate
200
on each side of the gate
202
. One source/drain terminal
206
is electrically connected to a trench capacitor structure
208
. Another source/drain terminal
206
is electrically connected to a bit line
210
. A conventional trench capacitor
208
has a three-layered structure that includes a conductive layer, a dielectric layer and another conductive layer. The entire trench capacitor structure
208
is embedded inside the substrate
200
.
FIG. 3
is a circuit diagram showing the memory cell design of a conventional synchronous dynamic random access memory.
FIG. 4
is the circuit diagram of a conventional sense amplifier. Using the sense amplifier in
FIG. 4
to extract data from the capacitor involves the following steps. First, voltage equalizing transistor EQL equalizes the voltage at the bit line BL and /BL and then sets their voltage to a pre-defined voltage level VEQ. Thereafter, the transistor EQL is shut off and then the word line WL
0
transmits a read signal to the control transistor N linked to the capacitor C. The capacitor C charges up the word line /BL (if the capacitor C stores positive charges) so that voltage level of the bit line /BL reaches VEQ+&Dgr;V. At this moment, voltage level of the bit line BL is still maintained at VEQ. After charging up the bit line /BL, the gate of both the P-type transistor P
1
and the N-type transistor N
1
are at a voltage level VEQ+&Dgr;V and the gate of both the P-type transistor P
2
and the N-type transistor N
2
are at a voltage level VEQ. The bias voltage applied to the transistors N
2
and P
2
is VEQ and the bias voltage applied to the transistor N
1
and P
1
is VEQ+&Dgr;V. This will lead to the gradual shutdown of the low VT transistors N
2
and P
1
through the slow opening of the low VT transistors N
1
and P
2
due to the external voltage VDD and VSS. This process is continued until the transistors N
1
and P
2
are completely open and the transistors N
2
and P
1
are completely close. Thereafter, a voltage from a column decoder is transmitted to the gate terminal of the N-type transistors N
3
and N
4
. The voltage source VSS will output a voltage level to a data line (Data) via the transistor N
1
and the voltage source VDD will output a voltage level to a data line (/Data) via the transistor P
2
. Through the signals on the data lines (Data and /Data), the data value (a data value of ‘1’ or ‘0’) stored inside the capacitor C can be determined.
According to
FIG. 3
, when the sense amplifier X attempts to read out memory cell data, the reading operation may lead to a drop or a rise in the voltage of the memory cell in excess of or in short of the base voltage necessary to determine the next ‘0’ or ‘1’ data value. However, as BL and /BL are pulled towards VDD and VSS, the memory cell is undergoing a data refresh operation to ensure a normal operation the next time. Using memory read from the memory cell A as an example, the word line WL
0
will remain in an open state during the read operation and the sense amplifier X will select bit line BL
1
and read out the data inside the memory cell A. Furthermore, after the read-out operation, the sense amplifier X will perform a data refresh operation of the memory cell again.
If the dash-line circled section underneath the memory cell A in
FIG. 3
has another memory cell B, the word line WL
0
will open up both memory cell A and memory cell B in the process of reading data from memory cell A. Due to some limitations of the sense amplifier X circuit (as shown in FIG.
3
), there are two major problems. Firstly, the opened memory cell A and memory cell B prevents the executing of the refresh operation. Secondly, signals from memory cell A and memory B may divert to BL
1
and /BL
1
, when the word line WL
0
switches open the memory cell A and the memory cell B at the same time. If the signals to the bit lines BL
1
and /BL
1
flows in the same direction (that is, both are at logic level ‘0’ or ‘1’), the sense amplifier is prevented from operation. On the contrary, if the signals to the bit lines BL
1
and /BL
1
flows in opposite direction (one at logic level ‘0’ and the other at logic level ‘1’), the user cannot decide whether the signal comes from memory cell A or the memory cell B. In other words, if a memory cell is located within the dash-line circle, repeated selection of bit line may lead to a failure to refresh some portion of the memory cell or the production of read-out errors.
As shown in
FIG. 3
, the sense amplifier X is designed with the concept that both bit line BL and bit line /BL lie along the same X-coordinate, no matter if the SDRAM has stack capacitor or a trench capacitor. Moreover, each sense amplifier X is capable of controlling bit lines BL
0
, /BL
0
, BL
1
and /BL
1
. In addition, because of circuit limitation of the sense amplifier X and consideration regarding wafer fabrication, useful memory cells are located inside the solid circle portion only. That means, in designing the layout of an integrated circuit, the dash-line circle portion in
FIG. 3
must be free of any memory cell. Since some areas must be vacated in this type of circuit layout design, wafer areas are wasted.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to

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