Synchronous dynamic random access memory for stabilizing a redun

Details Synchronous dynamic random access memory for stabilizing a redun Synchronous dynamic random access memory for stabilizing a redun

1998-06-26

1999-09-14

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, 3652257, 365233, G11C 700

Patent

active

059532670

ABSTRACT:
A synchronous dynamic random access memory (DRAM) for stabilizing a redundant operation prevents a redundant decoder's malfunction which occurs in a step of latching a redundant decoder according to a fuse programmable information during a power-up time. The synchronous DRAM for stabilizing a redundant operation includes: a column address pre-decoder which generates a plurality of decoded addresses needed by the column decoder, and connects them to a corresponding column decoder; a redundant column pre-decoder which generates a fuse-programmable address needed by the spare column decoder; a row address pre-decoder which generates a plurality of decoded addresses needed by the row decoder, and connects them to a corresponding row decoder; a redundant row pre-decoder which generates a fuse-programmable address needed by the spare row decoder; and a redundant enable signal generator which generates a global enable signal for driving both the redundant row pre-decoder and the redundant column pre-decoder, after a plurality of address inputs and a power-supply voltage being input to both the redundant column pre-decoder and the redundant row pre-decoder are reached to a stable state.

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