Synchronous dynamic random access memory architecture for sequen

Details Synchronous dynamic random access memory architecture for sequen Synchronous dynamic random access memory architecture for sequen

1997-12-19

2000-10-24

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711127, 711157, G06F 1200

Patent

active

061382140

ABSTRACT:
An electronic memory device which includes a memory array having a plurality of memory cells arranged into a plurality of units. Each unit is divided into a first portion including only even addressed memory cells and a second portion including only odd addressed memory cells. A column decoder and row decoder are coupled to the memory array for selecting a number of the plurality of memory cells. A sense amplifier is coupled to the memory array for performing read and write operations from the selected memory cells. An address line is split for application of a split address to said even and odd addressed memory cells.

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"16Mbit Synchronous DRAM with 125Mbyte/sec Data Rate," Yunho Choi et al., pp. 65-66.

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