Synchronous dual port ram

Details Synchronous dual port ram Synchronous dual port ram

1995-02-10

1996-10-15

Nelms, David C.

Static information storage and retrieval

Addressing

Multiple port access

365210, 36518908, 326 38, G11C 800, G11C 700

Patent

active

055661238

ABSTRACT:
A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, thereby dramatically increasing the speed of applications using the two sets of RAM. A CLB in the synchronous mode latches the appropriate address and data signals, and generates a strobed write enable signal. The strobed signal is self-timed, i.e. the write operation is fully automatic, thereby ensuring that a write operation occurs within one clock cycle.

REFERENCES:
patent: 5336950 (1994-08-01), Popli et al.
patent: 5349250 (1994-09-01), New
patent: 5425036 (1995-06-01), Liu et al.
patent: 5448522 (1995-09-01), Huang

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