Synchronous DRAM with selectable internal prefetch size

Details Synchronous DRAM with selectable internal prefetch size Synchronous DRAM with selectable internal prefetch size

2005-05-17

2005-05-17

Moazzami, Nasser (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S105000, C711S167000, C712S207000

Reexamination Certificate

active

06895474

ABSTRACT:
A synchronous memory device and its method of operation which can be set to operate at a plurality of supported prefetch modes. The prefetch mode may be set by programming a portion of a mode register of the memory device or by setting one or more programmable elements. For read operations, the synchronous memory device internally reads data corresponding to the largest supported prefetch size, and outputs read data corresponding to the current mode. For write operations the synchronous memory accepts write data corresponding to the selected prefetch mode and writes the received data to the array. Data words corresponding to data not received are masked from writing via a write masking circuit.

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Chen, “An Effective Programmable Prefetch Engine for On-Chip Caches”, ©1995 IEEE, p. 237-242.*
Chiueh, “Sunder: A Programmable Hardware Prefetch Architecture for Numerical Loops”, ©1994, IEEE, p. 488-497.

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