Synchronous DRAM utilizable as shared memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area

Reexamination Certificate

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C711S105000, C711S156000

Reexamination Certificate

active

06862667

ABSTRACT:
A memory array is divided into a plurality of blocks. A plurality of mode storage units is so disposed as to correspond to the memory blocks. When a plurality of controllers outputs a mode setting instruction at the time of making of power, a setting unit113sets control information designated by the mode setting instruction to the corresponding mode storage unit. When different controllers gain access to a synchronous DRAM, an access operation is executed for the corresponding memory block in accordance with the control information.

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patent: 5574876 (1996-11-01), Uchiyama et al.
patent: 6028816 (2000-02-01), Takemae et al.
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patent: 6173356 (2001-01-01), Rao
patent: 6205516 (2001-03-01), Usami
patent: 6401176 (2002-06-01), Fadavi-Ardekani et al.

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