Synchronous DRAM performing refresh operation a plurality of tim

Details Synchronous DRAM performing refresh operation a plurality of tim Synchronous DRAM performing refresh operation a plurality of tim

1995-11-13

1996-10-15

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Data refresh

36523006, 365233, G11C 700, G11C 800

Patent

active

055661190

ABSTRACT:
A semiconductor memory device is disclosed as a synchronous DRAM. This DRAM includes a refresh control circuit 4, 5 responding to a refresh request RF supplied thereto and performing a refresh operation at least twice. In the first refresh operation, one of word lines WL is selected and memory cells 13 associated with the selected word line are refreshed, and thereafter a different one of the word lines WL is selected and memory cells 13 associated therewith are refreshed in the next refresh operation.

REFERENCES:
patent: 5446696 (1995-08-01), Ware et al.
patent: 5511033 (1996-04-01), Jung

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